MT46H64M16LFBF-5 IT:B TR 原装 LPDDR

MT46H64M16LFBF-5 IT:B TR 原装  Mobile LPDDR

? VDD/VDDQ = 1.70–1.95V

? Bidirectional data strobe per byte of data (DQS)

? Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle

? Differential clock inputs (CK and CK#)

? Commands entered on each positive CK edge

? DQS edge-aligned with data for READs; centeraligned with data for WRITEs

? 4 internal banks for concurrent operation

? Data masks (DM) for masking write data; one mask per byte

? Programmable burst lengths (BL): 2, 4, 8, or 16

? Concurrent auto precharge option is supported

? Auto refresh and self refresh modes

? 1.8V LVCMOS-compatible inputs

? Temperature-compensated self refresh (TCSR)

? Partial-array self refresh (PASR)

? Deep power-down (DPD)

? Status read register (SRR)

? Selectable output drive strength (DS)

? Clock stop capability

? 64ms refresh, 32ms for automotive temperature

优势出，有需要的欢迎联系 

MT29F64G08CBABAWP固带 10K 23+

KLM8G1GETF-B041 10K 23+

KLMBG2JETD-B041 10K 23+

KLMAG1JETD-B041 10K 23+

K4E6E304EC-EGCG 10K 23+

K4B4G1646E-BCNB 10K 23+

K4F6E3S4HM-MGCJ 10K 23+

K4AAG165WA-BCWE 10K 23+

K4B4G0846E-BCNB 10K 23+

H5TC4G83BFR-PBA 95 17+

H26M41204HPR 5 20+

SDTNRGAMA-008G 35 21+

K4UBE3D4AA-MGCL 10K 23+

K4UBE3D4AB-MGCL 10K 23+

K4U6E3S4AA-MGCR 10K 23+