SDRAM存储器MT48LC16M16A2P-6A

MT48LC16M16A2P-6A  MT48LC16M16A2P-6A  MT48LC16M16A2P-6A

MT48LC16M16A2P-6A Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal, pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AAT devices)

• Auto refresh

– 64ms, 8192-cycle (commercial and industrial)

– 16ms, 8192-cycle (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• AEC-Q100

• PPAP submission

• 8D response time

Options Marking

• Configurations

– 64 Meg x 4 (16 Meg x 4 x 4 banks) 64M4

– 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8

– 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16

• Write recovery ( t WR)

–

t WR = 2 CLK

A2

• Plastic package – OCPL 1

– 54-pin TSOP II OCPL 1 (400 mil)

(standard)

TG

Options Marking

– 54-pin TSOP II OCPL 1 (400 mil)

Pb-free

P

– 60-ball FBGA (x4, x8) (8mm x 16mm) FB

– 60-ball FBGA (x4, x8) (8mm x 16mm)

Pb-free

BB

– 54-ball VFBGA (x16) (8mm x 14 mm) FG 2

– 54-ball VFBGA (x16) (8mm x 14 mm)

Pb-free

BG 2

– 54-ball VFBGA (x16) (8mm x 8 mm) F4 3

– 54-ball VFBGA (x16) (8mm x 8 mm)

Pb-free

B4 3

• Timing – cycle time

– 6ns @ CL = 3 (x8, x16 only) -6A

– 7.5ns @ CL = 3 (PC133) -75

– 7.5ns @ CL = 2 (PC133) -7E

• Self refresh

– Standard None

– Low power L 4

• Operating temperature range

– Industrial (–40˚C to +85˚C) AIT

– Automotive (–40˚C to +105˚C) AAT 4

• Revision :D/:G

Notes: 1. Off-center parting line.

2. Only available on Revision D.

3. Only available on Revision G.

4. Contact Micron for availability.