SDRAM存储器MT41K256M16HA-125:E

MT41K256M16HA-125:E  MT41K256M16HA-125:E  MT41K256M16HA-125:E  MT41K256M16HA-125:E

Description

DDR3L SDRAM (1.35V) is a low voltage version of the

DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V)

SDRAM data sheet specifications when running in

1.5V compatible mode.

Features

• V DD = V DDQ = 1.35V (1.283–1.45V)

• Backward compatible to V DD = V DDQ = 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• T C  of 0°C to +95°C

– 64ms, 8192-cycle refresh at 0°C to +85°C

– 32ms at +85°C to +95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

Options Marking

• Configuration

– 1 Gig x 4 1G4

– 512 Meg x 8 512M8

– 256 Meg x 16 256M16

• FBGA package (Pb-free) – x4, x8

– 78-ball (10.5mm x 12mm) Rev. D RA

– 78-ball (9mm x 10.5mm) Rev. E, J RH

• FBGA package (Pb-free) – x16

– 96-ball (10mm x 14mm) Rev. D RE

– 96-ball (9mm x 14mm) Rev. E HA

• Timing – cycle time

– 1.071ns @ CL = 13 (DDR3-1866) -107

– 1.25ns @ CL = 11 (DDR3-1600) -125

– 1.5ns @ CL = 9 (DDR3-1333) -15E

– 1.875ns @ CL = 7 (DDR3-1066) -187E

• Operating temperature

– Commercial (0°C ≤ T C ≤ +95°C) None

– Industrial (–40°C ≤ T C ≤ +95°C) IT