IS43DR16128C-25DBLI 随机存取存储器

IS43DR16128C-25DBLI

动态随机存取存储器 DDR2,2G,1.8V, RoHs 400MHz,128Mx16, IT

256Mx8, 128Mx16 DDR2 DRAM

DESCRIPTION IS43DR16128C-25DBLI

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate

architecture to achieve high-speed operation. The

double-data rate architecture is essentially a 4n-prefetch

architecture, with an interface designed to transfer two

data words per clock cycle at the I/O balls.

FEATURES IS43DR16128C-25DBLI

• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Double data rate interface: two data transfers

per clock cycle

• Differential data strobe (DQS, DQS)

• 4-bit prefetch architecture

• On chip DLL to align DQ and DQS transitions

with CK

• 8 internal banks for concurrent operation

• Programmable CAS latency (CL) 3, 4, 5, 6, and

7 supported

• Posted CAS and programmable additive latency

(AL) 0, 1, 2, 3, 4, 5, and 6 supported

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength, full and

reduced strength options

• On-die termination (ODT)

OPTIONS IS43DR16128C-25DBLI

• Configuration(s):

256Mx8 (32Mx8x8 banks) IS43/46DR82560C

128Mx16 (16Mx16x8 banks) IS43/46DR16128C

• Package:

x8: 60-ball BGA (8mm x 10.5mm)

x16: 84-ball WBGA (8mm x 12.5mm)

Timing – Cycle time

2.5ns @CL=5 DDR2-800D

3.0ns @CL=5 DDR2-667D

• Temperature Range:

Commercial (0°C ≤ Tc ≤ 85°C)

Industrial (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A1 (-40°C ≤ Tc ≤ 95°C; -40°C ≤ Ta ≤ 85°C)

Automotive, A2 (-40°C ≤ Tc; Ta ≤ 105°C)

Tc = Case Temp, Ta = Ambient Temp