LCMXO640C-3TN100C FPGA

LCMXO640C-3TN100C

FPGA - 现场可编程门阵列 640 LUTS 74 I/O

Introduction LCMXO640C-3TN100C

The MachXO is optimized to meet the requirements of

applications traditionally addressed by CPLDs and low

capacity FPGAs: glue logic, bus bridging, bus interfacing,

power-up control, and control logic. These devices

bring together the best features of CPLD and FPGA

devices on a single chip.

Features LCMXO640C-3TN100C

 Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single chip, no external configuration memory

required

• Excellent design security, no bit stream to

intercept

• Reconfigure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable

through JTAG port

• Supports background programming of

non-volatile memory

 Sleep Mode LCMXO640C-3TN100C

• Allows up to 100x static current reduction

 TransFR™ Reconfiguration (TFR)

• In-field logic update while system operates

 High I/O to Logic Density

• 256 to 2280 LUT4s

• 73 to 271 I/Os with extensive package options

• Density migration supported

• Lead free/RoHS compliant packaging

 Embedded and Distributed Memory

• Up to 27.6 Kbits sysMEM™ Embedded Block RAM

• Up to 7.7 Kbits distributed RAM

• Dedicated FIFO control logic