LC4256V-5TN144C CPLD Lattice

LC4256V-5TN144C

CPLD - 复杂可编程逻辑器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD

3.3 V/2.5 V/1.8 V In-System Programmable  SuperFAST High Density PLDs

Overview LC4256V-5TN144C

The LC4256V-5TN144C ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which contain multiple I/O cells. This architecture is shown in Figure 1.

Features LC4256V-5TN144C

 High Performance

• fMAX = 400 MHz maximum operating frequency

• tPD = 2.5 ns propagation delay

• Up to four global clock pins with programmable

clock polarity control

• Up to 80 PTs per output

 Ease of Design

• Enhanced macrocells with individual clock,

reset, preset and clock enable controls

• Up to four global OE controls

• Individual local OE control per I/O pin

• Excellent First-Time-FitTM and refit

• Fast path, SpeedLockingTM Path, and wide-PT path

• Wide input gating (36 input logic blocks) for fast

counters, state machines and address decoders

 Zero Power (ispMACH 4000Z) and Low

Power (ispMACH 4000V/B/C)

• Typical static current 10 μA (4032Z)

• Typical static current 1.3 mA (4000C)

• 1.8 V core low dynamic power

• ispMACH 4000Z operational down to 1.6 V VCC