存储器， DRAM IC,4G,AS4C256M16D3B-12BCN

数据列表 AS4C256M16D3B-12BCN/AS4C256M16D3B-12BCN

标准包装   180

包装   托盘  

产品族 存储器

存储器格式 DRAM

技术 SDRAM - DDR3

存储容量 4Gb （256M x 16）

存储器接口 并联

时钟频率 800MHz

写周期时间 - 字，页 15ns

访问时间 20ns

电压 - 电源 1.425V ~ 1.575V

工作温度 0°C ~ 95°C（TC）

安装类型 表面贴装

封装/外壳 96-TFBGA

AS4C256M16D3B-12BCN封装 96-FBGA（13.5x9）

AS4C256M16D3B-12BCN描述

Specifications

- Density : 4G bits

- Organization : 32M words x 16 bits x 8 banks

- Package :

- 96-ball FBGA

- Lead-free (RoHS compliant) and Halogen-free

- Power supply : VDD, VDDQ = 1.5V ± 0.075V

- Data rate :

- 1600Mbps

- 2KB page size

- Row address: A0 to A14

- Column address: A0 to A9

- Eight internal banks for concurrent operation

- Burst lengths (BL) : 8 and 4 with Burst Chop (BC)

- Burst type (BT) :

- Sequential (8, 4 with BC)

- Interleave (8, 4 with BC)

- CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11

- CAS Write Latency (CWL) : 5, 6, 7, 8

- Precharge : auto precharge option for each burst access

- Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)

- Refresh : auto-refresh, self-refresh

- Refresh cycles : - Average refresh period

7.8 μs at -40°C ≤ Tc ≤ +85°C

3.9 μs at +85°C < Tc ≤ +95°C

- Operating case temperature range

- Commercial Tc = 0°C to +95°C

Features

- Double-data-rate architecture; two data transfers per clock

cycle

- The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

- Bi-directional differential data strobe (DQS and DQS) is

transmitted/received with data for capturing data at the receiver

- DQS is edge-aligned with data for READs; center-aligned

with data for WRITEs

- Differential clock inputs (CK and CK)

- DLL aligns DQ and DQS transitions with CK transitions

- Commands entered on each positive CK edge; data and

data mask referenced to both edges of DQS

- Data mask (DM) for write data

- Posted CAS by programmable additive latency for better

command and data bus efficiency

- On-Die Termination (ODT) for better signal quality

- Synchronous ODT

- Dynamic ODT

- Asynchronous ODT

- Multi Purpose Register (MPR) for pre-defined pattern read

out

- ZQ calibration for DQ drive and ODT

- Programmable Partial Array Self-Refresh (PASR)

- RESET pin for Power-up sequence and reset function

- SRT range : Normal/extended

- Programmable Output driver impedance control

AS4C256M16D3B-12BCN图片