NT5AD512M16A4-HR 原装全新DDR4

NT5AD512M16A4-HR  原装全新DDR4

Data Integrity

- Auto Self Refresh (ASR) by DRAM built-in TS

- Auto Refresh and Self Refresh Modes

l DRAM Access Bandwidth

- Separated IO gating structures by Bank Groups

- Self Refresh Abort

- Fine Granularity Refresh

l Signal Synchronization

- Write Leveling via MR settings1

- Read Leveling via MPR

l Reliability & Error Handling

- Command/Address Parity

- Databus Write CRC

- MPR readout

- Boundary Scan (X16)

- Post Package Repair

Signal Integrity

- Internal VREFDQ Training

- Read Preamble Training

- Gear Down Mode

- Per DRAM Addressability

- Configurable DS for system compatibility

- Configurable On-Die Termination

- Data bus inversion (DBI)

- ZQ Calibration for DS/ODT impedance accuracy

via external ZQ pad (240 Ω ± 1%)

l Power Saving & Efficiency

- POD with VDDQ termination

- Command/Address Latency (CAL)

- Maximum Power Saving

- Low-power Auto Self Refresh (LPASR)

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