MT41K512M16VRP-107 IT:P TR 原装 LPDDR3

MT41K512M16VRP-107 IT:P TR全新原装 LPDDR3

? Uses two x8, 4Gb Micron die to make one x16 package

– Single rank TwinDie

– One external ZQ ball and one internal ZQ connected to VSSQ through an embedded serial resistor

? VDD = VDDQ = 1.35V (1.283–1.45V)

? Backward compatible to VDD = VDDQ = 1.5V ±0.075V

? Differential bidirectional data strobe

? 8n-bit prefetch architecture

? Differential clock inputs (CK, CK#)

? 8 internal banks

? Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

? Programmable CAS (READ) latency (CL)

? Programmable posted CAS additive latency (AL)

? Programmable CAS (WRITE) latency (CWL)

? Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

? Selectable BC4 or BL8 on-the-fly (OTF)

? Self refresh mode

? TC of –40°C to +105°C

– 64ms, 8192-cycle refresh at –40°C to +85°C

– 32ms at +85°C to +105°C

? Self refresh temperature (SRT)

? Automatic self refresh (ASR)

? Write leveling

? Multipurpose register

? Output driver calibration

? AEC-Q100

? PPAP submission

? 8D response time

MT29F64G08CBABAWP固带 10K 23+

KLM8G1GETF-B041 10K 23+

KLMBG2JETD-B041 10K 23+

KLMAG1JETD-B041 10K 23+

K4E6E304EC-EGCG 10K 23+

K4B4G1646E-BCNB 10K 23+

K4F6E3S4HM-MGCJ 10K 23+

K4AAG165WA-BCWE 10K 23+

K4B4G0846E-BCNB 10K 23+

K4UBE3D4AA-MGCL 10K 23+

K4UBE3D4AB-MGCL 10K 23+

K4U6E3S4AA-MGCR 10K 23+

全新原包原装可含税（香港可交）