MT40A512M16LY-075:E 全新原装 DDR4 存储IC

MT40A512M16LY-075:E 全新原装 DDR4 存储IC

? VDD = VDDQ = 1.2V ±60mV

? VPP = 2.5V, –125mV/+250mV

? On-die, internal, adjustable VREFDQ generation

? 1.2V pseudo open-drain I/O

? TC maximum up to 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

? 16 internal banks (x4, x8): 4 groups of 4 banks each

? 8 internal banks (x16): 2 groups of 4 banks each

? 8n-bit prefetch architecture

? Programmable data strobe preambles

? Data strobe preamble training

? Command/Address latency (CAL)

? Multipurpose register READ and WRITE capability

? Write leveling

? Self refresh mode

? Low-power auto self refresh (LPASR)

? Temperature controlled refresh (TCR)

? Fine granularity refresh

? Self refresh abort

? Maximum power saving

? Output driver calibration

? Nominal, park, and dynamic on-die termination(ODT)

? Data bus inversion (DBI) for data bus

? Command/Address (CA) parity

? Databus write cyclic redundancy check (CRC)

? Per-DRAM addressability

? Connectivity test

? sPPR and hPPR capability

? JEDEC JESD-79-4 compliant

MT29F64G08CBABAWP固带 10K 23+

KLM8G1GETF-B041 10K 23+

KLMBG2JETD-B041 10K 23+

KLMAG1JETD-B041 10K 23+

K4E6E304EC-EGCG 10K 23+

K4B4G1646E-BCNB 10K 23+

K4F6E3S4HM-MGCJ 10K 23+

K4AAG165WA-BCWE 10K 23+

K4B4G0846E-BCNB 10K 23+

H5TC4G83BFR-PBA 95 17+

H26M41204HPR 5 20+

SDTNRGAMA-008G 35 21+

K4UBE3D4AA-MGCL 10K 23+

K4UBE3D4AB-MGCL 10K 23+

K4U6E3S4AA-MGCR 10K 23+

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