FPGA视频协议开发技术在LatticeECP3设计的应用

 

　　Lattice公司的LatticeECP3 Versa评估板使设计者能评价和实验LatticeECP3现场可编门阵列，而LatticeECP3系列可提供高性能的特性如增强DSP架构，高速SERDES和FPGA中高速源同步接口，这些特性使得LatticeECP3系列非常适合用在量大高速低成本的产品如工业网络，工厂自动化，计算，医疗设备，国防和消费类电子。

　　Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells （PIC）。 Interspersed between the rows of logic blocks are rows of sysMEM? Embedded Block RAM （EBR） and rows of sys- DSP? Digital Signal Processing slices, as shown in Figure 2-1. The LatticeECP3-150 has four rows of DSP slices; all other LatticeECP3 devices have two rows of DSP slices. In addition, the LatticeECP3 family contains SERDES Quads on the bottom of the device. There are two kinds of logic blocks, the Programmable Functional Unit （PFU） and Programmable Functional Unit without RAM （PFF）。 The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a twodimensional array. Only one type of block is used per row. The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated 18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES （Serializer / Deserializer） channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of four SERDES channels, along with its Physical Coding Sub-layer （PCS） block, creates a quad. The functionality of the SERDES/PCS quads can be controlLED by memory cells set during device configuration or by registers that are addressable during device operation. The registers in every quad can be programmed via the SERDES Client Interface （SCI）。 These quads （up to four） are located at the bottom of the devices. Each PIC block encompasses two PIOs （PIO pairs） with their respective sysI/O buffers. The sysI/O buffers of the LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1 LVDS, along with memory interfaces including DDR3. Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two Delay Locked Loops （DLLs） and up to ten Phase Locked Loops （PLLs）。 The PLL and DLL blocks are located at the end of the EBR/DSP rows. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family supports a sysCONFIG? port located in the corner between banks one and two, which allows for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error detect capability. The LatticeECP3 devices use 1.2V as their core voltage.

　　LatticeECP3主要特性：

　　Higher Logic Density for Increased System Integration

　　17K to 149K LUTs

　　133 to 586 I/Os

　　Embedded SERDES

　　150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit SERDES, and 8-bit SERDES modes

　　Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols

　　Up to 16 channels per device: PCI Express, SONET/SDH, Ethernet （1GbE, SGMII, XAUI）， CPRI, SMPTE 3G and Serial RapidIO

　　sysDSP

　　Fully cascadable slice architecture

　　12 to 160 slices for high performance multiply and accumulate

　　Powerful 54-bit ALU operations

　　Time Division Multiplexing MAC Sharing

　　Rounding and truncation

　　Each slice supports

　　–Half 36x36, two 18x18 or four 9x9 multipliers

　　–Advanced 18x36 MAC and 18x18 Multiply-Multiply-Accumulate （MMAC） operations

　　Flexible Memory Resources

　　Up to 6.85Mbits sysMEM  Embedded Block RAM （EBR）

　　36K to 303K bits distributed RAM

　　sysCLOCK Analog PLLs and DLLs

　　Two DLLs and up to ten PLLs per device

　　Pre-Engineered Source Synchronous I/O

　　DDR registers in I/O cells

　　Dedicated read/write levelling functionality

　　Dedicated gearing logic

　　Source synchronous standards support

　　–ADC/DAC, 7:1 LVDS, XGMII

　　–High Speed ADC/DAC devices

　　Dedicated DDR/DDR2/DDR3 memory with DQS support

　　Optional Inter-Symbol Interference （ISI）   correction on outputs

　　Programmable sysI/O  Buffer Supports Wide Range of Interfaces

　　On-chip termination

　　Optional equalization filter on inputs

　　LVTTL and LVCMOS 33/25/18/15/12

　　SSTL 33/25/18/15 I, II

　　HSTL15 I and HSTL18 I, II

　　PCI and Differential HSTL, SSTL

　　LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS

　　Flexible Device Configuration

　　Dedicated bank for configuration I/Os

　　SPI boot flash interface

　　Dual-boot images supported

　　Slave SPI

　　TransFR  I/O for simple field updates

　　Soft Error Detect embedded macro

　　System Level Support

　　IEEE 1149.1 and IEEE 1532 compliant

　　Reveal Logic Analyzer

　　ORCAstra FPGA configuration utility

　　On-chip oscillator for initialization & general use

　　1.2V core power supply

　　LatticeECP3 系列选择指引表：

图1。LatticeECP3-35简化方框图（顶层）

　　LatticeECP3视频协议板

　　LatticeECP3 Video Protocol Board

　　The LatticeECP3? FPGA family includes many features for video applications. For example, DisplayPort, SMPTE standards （SD-SDI, HD-SDI and 3G-SDI）， DVB-ASI, DVI and HDMI can be implemented with 16 channels of embedded SERDES/PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the generic DDRX2 mode on the I/O pins. When configuring to TRLVDS mode, the I/O pins on banks 0 and 1 can also be used to receive the TMDS signals of DVI or HDMI video standard.

　　This user's guide describes revision C of the LatticeECP3 Video Protocol Board featuring the LatticeECP3 LFE3-95E-7FN1156C FPGA device. The stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of many different video applications.

图2。LatticeECP3视频协议板外形图-Rev.C

　　主要特性：

　　Video interfaces for interconnection to video standard equipment

　　Allow the demonstration of SD/HD/3G-SDI, DisplayPort and PCI Express （x4） interfaces using SERDES channels

　　High speed Mezzanine connector connected to SERDES channels for future expansion

　　Allows the demonstration of LVDS video standards – ChannelLink and CameraLink

　　Allows control of SERDES PCS registers using the Serial Client Interface （ORCAstra）

　　Allows the demonstration of receiving TMDS signals using the DVI interface

　　On-board Boot Flash with Serial SPI Flash memory device

　　Shows interoperation with high performance DDR2 memory components

　　Driver-based "run-time" device configuration capability via an ORCAstra or RS232 interface

　　SMAs for external high-speed clock / PLL inputs

　　Switches, LEDs and LCD display header for demo purposes

　　Mictor connector for using Logic Analyzer in the debugging phase

　　Input connection for lab-power supply

　　Power connections and power sources

　　ispVM  programming support

　　On-board and external reference clock sources

　　Various high-speed layout structures

　　User-defined input and output points

　　Performance monitoring via test headers, LEDs and switches

图3。LatticeECP3视频协议板-Rev. C功能框图

 图4。DisplayPort 视频接口方框图

图5。LatticeECP3视频协议板方框图

图6。LatticeECP3视频协议板电路图-电源

图7。LatticeECP3视频协议板电路图-电源管理

图8。LatticeECP3视频协议板电路图-FPGA电源

图9。LatticeECP3视频协议板电路图-FPGA配置

图10。LatticeECP3视频协议板电路图-SERDES

图11。LatticeECP3视频协议板电路图-DDR2存储器

图12。LatticeECP3视频协议板电路图-DVVLCD/RS232

图13。LatticeECP3视频协议板电路图-通路/照相机连接

图14。LatticeECP3视频协议板电路图-TI ADC/CLOCK

图15。LatticeECP3视频协议板电路图-LED/开关

图16。LatticeECP3视频协议板电路图-SDI驱动/均衡器

图17。LatticeECP3视频协议板电路图-SDI基准时钟控制

图18。LatticeECP3视频协议板电路图-SRI Rx基准时钟

图19。LatticeECP3视频协议板电路图-SRI Tx基准时钟