Instantiating LPMs in Verilog

The example in this section defines a black box for an Altera LPM_RAM_DQ,
which is then instantiated at a higher level. The LPM_RAM_DQ is a parameterized
RAM with separate input and output ports. Altera recommends
using the LPM_RAM_DQ to implement asynchronous memory or memory
with synchronous inputs and/or outputs. The LPM_RAM_DQ function uses
EABs in FLEX10K devices, and latch arrays in other device families. If you
are using a FLEX10K device, Altera recommends that you use synchronous
rather than asynchronous RAM functions.
1. Define a black box with the name myram_64x16. Notice that
immediately after the port list, but before the semicolon ';' is the
syn_black_box synthesis directive with the LPM_TYPE specified as
LPM_RAM_DQ, along with other specified arguments.
module myram_64x16 (data, address, inclock, outclock, we, q)
/* synthesis syn_black_box
LPM_WIDTH=16
LPM_WIDTHAD=6
LPM_TYPE="LPM_RAM_DQ" */ ;
input [15:0] data;w
input [5:0] address;
input inclock, outclock;
input we;
output [15:0] q;
// This is an empty module
endmodule
2. Now instantiate the LPM in a higher-level module.
module myram(clock, we, data, address, q);
input clock, we;
input [15:0] data;
input [5:0] address;
output [15:0] q;
myram_64x16 inst1 (data, address, clock, clock, we, q);
endmodule