Some Rules for Matching

Rules for MOS Transistor Matching

·Minimal matching:

Typical three-sigma drain current mismatches of several percent. Minimal matching is often used for constructing bias current networks that do not require any particular degree of precision . This level of matching corresponds to typical in excess of ±10m V and is therefore inadequate for voltage matching applications.

·Moderate matching :

Typical three-sigma offset voltage of ±5m V or drain current mismatches of less than ±1%. Useful for constructing input stages of non-critical op-amps and comparators ,where untrimmed offsets of ±10m V can be maintained.

·Precise matching:

Typical three-sigma offset voltages of less than ±1m V or drain current mismatches of less than ±0.1%. This level of matching usually involves trimming, and the resulting circuit will probably meet specification within only a limited range of temperatures due to the presence of uncompensated temperature variations.

The following rules summarize the most important principles of MOS transistor matching:

1. Use identical finger geometries

2. Use large active areas

3. For voltage matching, keep Vgst small

4. For current matching, keep Vgst large

5. Orient transistor in the same direction

6. Place transistors in close proximity

7. Keep the layout of the matched transistors as compact as possible

8. Where practical , use common-centroid layouts

9. Place dummy segments on the ends of arrayed transistors

10. Place transistors in areas of low stress gradients

11. Place transistors well away from power devices

12. Do not place contacts on top of active gate area

13. Do not route metal across the active gate region

14. Keep all junctions of deep diffusions far away from active gate area

15. Place precisely matched transistors on axes of symmetry of the die

16. Do not allow the NBL shadow intersect the active gate area

17. Connect gate fingers using metal straps

18. Use thin-oxide devices in preference to thick-oxide devices

19. Consider using NMOS transistor rather than PMOS transistor

Rules for Device Matching

·Minimal matching:

Approximately ±1% three-sigma mismatch, or 6 to 7 bits of resolution. Suitable for general-purpose use, such as for degenerating current mirrors in biasing circuitry.

·Moderate matching :

Approximately ±0.1% three-sigma mismatch, or 9 to 10 bits of resolution. Suitable for ±1% bandgap references, op-amp and comparator input stages, and most other analog applications.

·Precise matching:

Approximately ±0.01% three-sigma mismatch, or 13 to 14 bits of resolution. Suitable for precision A/D and D/A converters and for all other applications requiring extreme precision. Capacitors can more easily obtain this level of matching than resistors.

² Rules for Resistor Matching :

Minimal matching can be obtained without much difficulty, and moderate matching can be reliably obtained using interdigitation. Precisely matched resistors are difficult to construct due to variations in contact resistance and the presence of thermal and stress gradients. The following rules summarize the most important principles of resistor layout design.

1. Construct matched resistors from a single material

2. Make matched resistors the same width

3. Make matched resistors sufficiently wide

4. Where practical, use identical geometries for resistors

5. Orient matched resistors in the same direction

6. Place matched resistors in close proximity

7. Interdigitate arrayed resistors

8. Place dummies on either end of a resistor array

9. Avoid short resistor segments

10. Connect matched resistors in order to cancel thermoelectrics

11. If possible, place matched resistors in low stress areas

12. Place matched resistors well away from power devices

13. Place precisely matched resistors on axes of symmetry of the die

14. Consider tank modulation effects

15. Sectioned resistors are superior to serpentines

16. Use ploy resistors in preference to diffused ones

17. Place deposited resistor over filed oxide

18. Chose P-type poly resistors in preference to N-type poly resistors

19. Do not allow the NBL shadow to intersect matched diffused resistors

20. Consider filed plating and electrostatic shielding

21. Avoid routing unconnected leads over matched resistors

22. If leads cross resistors, they should cross all resistors segments in the same manner

23. Avoid excessive power dissipation in matched resistors

² Rules for Capacitor Matching:

Properly constructed capacitor can obtain a degree of matching unequaled by any other integrated component. Matched capacitors form the bias of most data conversion produces such as A/D and D/A. Untrimmed oxide-dielectric capacitors packaged in plastic can achieve ±0.01% matching. This suffices to allow construction of 14-bit and perhaps even 15-bit converters. Beyond this, some type of wafer-level trimming is required to maintain accuracy. Matching of ±0.001% can be obtained using trimmed oxide-dielectric capacitors packaged in plastic, making possible 16 to 18-bit monolithic converters. High-precision products usually employ hybrid assemblies rather than single-die circuits.

1. Use identical geometries for matched capacitors

2. Use square geometries for precisely matched capacitors

3. Make matched capacitors as large as practical

4. Place matched capacitors adjacent to one another

5. Place matched capacitors over filed oxide

6. Connect the upper electrode of a matched capacitor to the higher-impedance node

7. Place dummy capacitors around the outer edge of the array

8. Electrostatically shield matched capacitors

9. Cross-couple arrayed capacitors

10. Consider the capacitance of leads connecting to the capacitor

11. Do not run leads over matched capacitors unless they are electrostatically shielded

12. Use thick-oxide dielectrics in preference to thin-oxide or composite dielectrics

13. If possible, place capacitors in areas of low stress gradients

14. Place matched capacitors well away from power device

15. Place precisely matched capacitors on axes of symmetry of the die