Active and Passive Devices

时间：2007-04-29

Active devices for R.F. include GaAs FETs, silicon bipolars and NMOS and possibly PMOS transistors. Standard library types for a given process vendor can usually be adapted to the requirement, and are strongly advocated to avoid layout errors.
Passive devices include resistors and capacitors, which are routinely included in both low and high frequency analogue circuits, and inductors, which are commonly included in GaAs circuits, but less so in silicon because the losses are greater.

Some sample device layouts are shown below:

Fig 2 : NMOS transistor, designed to a 2 lambda rule set, for 0.8 micron process

半导体技术天地[Semiconductor%20Technology%20World]芯片设计版图工艺制程封装测试wafer,chip,ic,process,layout,package,FA.files/3_AhHi0xo4XK70.jpg" onload="if(this.width>screen.width*0.7) {this.resized=true; this.width=screen.width*0.7; this.alt='Click here to open new window';}" border=0 onclick="if(this.resized) {window.open('https://ocean.bbs.topzj.com/attachments/m15//17/08/17083/forumid_22606/3_AhHi0xo4XK70.jpg');}">

One feature of many layout editors is the use of a 'lambda;' based rule set. The designs are all based on a convenient unit, for example the gate of the transistor above is 2 units wide. Then, at a given process foundry, this rule may be interpreted as required. For example, this design may be used on a 0.8 micron process, so the 2 units wide gate would be processed as 0.8 microns. This is primarily applicable to digital design, for easy transport of designs between processes, but the designer should be aware of this facility.

Fig 3 : PMOS transistor

Similarly, a PMOS device is shown above. In this case, the device is surrounded by an N-well, for correct polarity of conductors and isolation.

Fig 4 : Vertical NPN transistor

A more complex structure, not always available on MOS processes, is a vertical NPN bipolar transistor, as above. Again, a recommended layout from the process vendor should be used in this instance if possible.

Fig 5, Lateral PNP

Less good, especially in the R.F. context, is the lateral PNP shown above. PNPs in general have not been well used in R.F. circuits, but new processes offer Fts close to those expected from the NPNs, so interesting circuits might be made in this respect.

Fig 6 : Polysilicon resistor

For R.F. applications, polysilicon resistors are preferred, since they are deposited above the first oxide layers, and therefore have less capacitance to ground and other nodes than a similar value junction resistor. This ensures low parasitic capacitance. They are also voltage insensitive, although the temperature coefficient can be quite high, and should be carefully calculated, especially for the high sheet resistivities, which often have a negative coefficient.

Fig 7 : Poly1 - Poly2 capacitor

Capa

citors formed between the poly silicon layers ( Poly1 - poly2) are also preferred for R.F. applications. The reasoning is similar to that for the resistors. A rough rule is that the capacitance to ground from the bottom plate of the capacitor should be about 1/10 of the plate capacitance. Alternative sandwich capacitors such as metal to metal are usually poorer in this respect, although series resistance in the ploy1-poly2 type is an issue to be addressed.

Fig 8 : Inductor Layout

An inductor is the most difficult compromise in layout, and many papers have been written on this subject. The inductor above has some of the desirable features. These are:-

1. The centre is relatively open. Small turns add little inductance, just resistance and capacitance.
2. The turns are closely spaced, for minimum overall size. It may be improved by:-

3. Chamfered corners, although this is debated.
4. M2 instead of M1, because M2 is usually thicker and therefore lower resistance. M2 is alos lower capacitance to substrate. M3, when available is often better. This layout is from a chip where the M1 - M2 comparison is the subject of an experiment.
5. Larger central hole, although this may compromise size.

上一篇：Bond Pads

下一篇：将铝线烧断到底