半导体技术天地[Semiconductor%20Technology%20World]芯片设计版图工艺制程封装测试wafer,chip,ic,process,layout,package,FA.files/1_IG48SrdI3J2K.jpg" onload="if(this.width>screen.width*0.7) {this.resized=true; this.width=screen.width*0.7; this.alt='Click here to open new window';}" border=0 onclick="if(this.resized) {window.open('https://ocean.bbs.topzj.com/attachments/m15//17/08/17083/forumid_22606/1_IG48SrdI3J2K.jpg');}"> Many process vendors offer a choice of bond pads. At lower frequencies, the use of a static protected bond pad should be regarded as mandatory; the process vendor will offer such pads. At higher frequencies, the decisions are more difficult. Typically, static protection pads include some series resistance, possibly hundreds of ohms. Although not an issue in a digital circuit, clearly this would seriously degrade a low noise amplifier. A better choice would have no series resistance, and minimal capacitance. Some vendors offer smaller 'R.F.' pads, with minimal capacitance. These are often round rather than square, and typically have fewer protection components.
Component matching is less often required at R.F. than at lower frequencies, although symmetry of layout where it exists in the circuit should always be considered.
Connections to the outside world are particularly problematic for R.F. chips. The inductances and capacitances of the bond wires and lead frame usually give a far from ideal R.F. environment. There are 'R.F.' packages where these effects have been minimised, but they are expensive and little used in practice.
The table above quantifies some of the parasitic components in the connections to the outside. The bond pad capacitance can reach 4pF unles R.F. pads are used. Self and mutual inductance terms are important, since coupling between adjacent pins can occur. At frequencies of >2GHz, the isolation between adjacent pins may be less than 30dB. It is sometime advisable to include grounded pin/bond wire/pad combinations as shielding between sensitive nodes.
