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FEATURES
[ MCP ]
● Operation Temperature
- -30 o C ~ 85 o C
● Packcage
- 137-ball FBGA - 10.5x13.0mm 2 , 1.2t, 0.8mm pitch
- Lead & Halogen Free
[ NAND Flash ]
● Multiplane Architecture
● Supply Voltage
- Vcc = 1.7 - 1.95 V
● Memory Cell Array
- (1K + 32) words x 64 pages x 4096 blocks
● Page Size
- (1K+ 32 spare) Words
● Block Size
- (64K + 2K spare) Words
● Page Read / Program
- Random access : 25us (max.)
- Sequential access : 45ns (min.)
- Page program time : 250us (typ.)
- Multi-page program time (2 pages) : 250us (typ.)
● COPY BACK PROGRAM
- Automatic block download without latency time
● FAST BLOCK ERASE
- Block erase time: 3.5ms (typ.)
- Multi-block erase time (2 blocks) : 3.5ms (typ.)
● CACHE READ
- Internal (2048 + 64) Byte buffer to improve the read
throughtput.
● STATUS REGISTER
- Normal Status Register (Read/Program/Erase)
- Extended Status Register (EDC)
● BLOCK PROTECTION
- To Protect Block against Write/Erase
● HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions.
● DATA RETENTION
- 100,000 Program / Erase cycles (with 1bit /528Byte ECC)
- 10 Year Data retention
[ DDR SDRAM ]
● Double Data Rate architecture
- two data transfer per clock cycle
● x32 bus width
● Supply Voltage
- VDD / VDDQ = 1.7 - 1.95 V
● Memory Cell Array
- 16Mb x 4Bank x 32 I/O x 2 Die
● Bidirectional data strobe (DQS)
● Input data mask signal (DQM)
● Input Clock
- Differential Clock Inputs (CK, /CK)
● MRS, EMRS
- JEDEC Standard guaranteed
● CAS Latency
- Programmable CAS latency 2 or 3 supported
● Burst Length
- Programmable burst length 2 / 4 / 8 with both sequen-
tial and interleave mode
特征
[微软]
●操作温度
- 30 C 85 C ~
●packcage
137球FBGA封装- 10.5x13.0mm 2,1.2T,间距为0.8mm
铅和卤素自由
【NAND Flash ]
●多平面结构
●电源电压
- 1.7 - 1.95 V的VCC =
●存储器单元阵列
-(1K±32)字×64页×4096块
●页面大小
-(1K + 32备用)的话
●块大小
-(64K + 2K备用)的话
●页读/程序
随机访问:精度(最大)
顺序存取:45ns(分钟)
页的计划时间:250us(典型值。)
多页的编程时间(2页):250us(典型值。)
●回拷贝程序
没有延迟时间自动分块下载
●快速的块擦除
块擦除时间:3.5ms(典型值。)
多块擦除时间(2块):3.5ms(典型值。)
●缓存读取
内部(2048 + 64)字节缓冲区来提高阅读
吞吐量。
●状态寄存器
正常状态寄存器(读/编程/擦除)
扩展状态寄存器(EDC)
●块保护
为了保护块对写入/擦除
●硬件数据保护
编程/擦除的权力过渡期间锁定。
●数据保留
100000的编程/擦除周期(与1位/ 528byte ECC)
10年的数据保留
【DDR SDRAM ]
●双倍数据速率结构
两个数据传输每个时钟周期
●X32总线宽度
●电源电压
VDD / VDDQ = 1.7 - 1.95 V
●存储器单元阵列
- 16MB的X 4bank×32的I / O x 2死
●双向数据选通(DQS)
●输入数据掩蔽信号(DQM)
●输入时钟
差分时钟输入(CK,CK /)
●夫人,电子病历
- JEDEC标准保证
●CAS延迟
可编程延迟时间2或3支
●突发长度
可编程的突发长度的2 / 4 / 8与两个序列—
TiAl和交织模式
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