ALTERA复杂可编程逻辑器件EPM240T100I5N特征

ALTERA复杂可编程逻辑器件EPM240T100I5N特征

制造商零件编号：
EPM240T100I5N
制造商:
Intel / Altera
说明：
CPLD - 复杂可编程逻辑器件 CPLD - MAX II 192 Macro 80 IOs
规格
产品种类: CPLD - 复杂可编程逻辑器件
制造商: Intel
产品: MAX II
大电池数量: 192
逻辑数组块数量——LAB: 24
最大工作频率: 304 MHz
传播延迟—最大值: 4.7 ns
输入/输出端数量: 80 I/O
工作电源电压: 2.5 V, 3.3 V
最小工作温度: - 40 C
最大工作温度: + 85 C
封装 / 箱体: TQFP-100
商标: Intel / Altera
存储类型: Flash
逻辑元件数量: 240
工作电源电流: 55 mA
系列: EPM240
工厂包装数量: 90
电源电压-最大: 3.6 V
电源电压-最小: 2.375 V
总内存: 8192 bit
商标名: MAX II
单位重量: 600 mg
Introduction
The MAX® II family of instant-on, non-volatile CPLDs is based on a 0.18-μm,
6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128
to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. MAX II devices
offer high I/O counts, fast performance, and reliable fitting versus other CPLD
architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and
enhanced in-system programmability (ISP), MAX II devices are designed to reduce
cost and power while providing programmable solutions for applications such as bus
bridging, I/O expansion, power-on reset (POR) and sequencing control, and device
configuration control.
Features
The MAX II CPLD has the following features:
■ Low-cost, low-power CPLD
■ Instant-on, non-volatile architecture
■ Standby current as low as 25 μA
■ Provides fast propagation delay and clock-to-output times
■ Provides four global clocks with two clocks available per logic array block (LAB)
■ UFM block up to 8 Kbits for non-volatile storage
■ MultiVolt core enabling external supply voltages to the device of either
3.3 V/2.5 V or 1.8 V
■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
■ Bus-friendly architecture including programmable slew rate, drive strength,
bus-hold, and programmable pull-up resistors
■ Schmitt triggers enabling noise tolerant inputs (programmable per pin)
■ I/Os are fully compliant with the Peripheral Component Interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 66 MHz
■ Supports hot-socketing
■ Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry
compliant with IEEE Std. 1149.1-1990
■ ISP circuitry compliant with IEEE Std. 1532