The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V Vdd
and 3.3V Vddq memory systems containing 268,435,456
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is organized
as 8,192 rows by 512 columns by 16 bits or 8,192
rows by 1,024 columns by 8 bits.
The 256MbSDRAM includes anAUTOREFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during 。
