MPC8313VRAFFC 微处理器 NXP

MPC8313VRAFFC

微处理器 - MPU 8313 REV2.2 NO ENC

The MPC8313VRAFFC security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded  from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,  3DES, AES, SHA-1, and MD-5 algorithms.

MPC8313VRAFFC Features

The following features are supported in the MPC8313E:

• Embedded PowerPC™ e300 processor core built on Power Architecture™ technology; operates at up to 333 MHz.

• High-performance, low-power, and cost-effective host processor

• DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both DDR1 and DDR2

• 16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units

• Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced local bus interface with up to 66-MHz operation, and USB 2.0 (high speed) with an on-chip PHY.

Security Engine MPC8313VRAFFC

The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i®, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are as follows:

• Data encryption standard execution unit (DEU), supporting DES and 3DES

• Advanced encryption standard unit (AESU), supporting AES

• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and HMAC with any algorithm

• One crypto-channel supporting multi-command descriptor chains