MIMX8MQ6DVAJZAA 处理器 NXP

MIMX8MQ6DVAJZAA

处理器 - 专门应用 i.MX 8M Quad 17X17 no lid

The i.MX 8M Dual / 8M QuadLite / 8M Quad processors

processors.

Power supplies requirements and restrictions MIMX8MQ6DVAJZAA

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the processor (worst-case scenario)

Power-up sequence MIMX8MQ6DVAJZAA

The i.MX 8M Dual / 8M QuadLite / 8M Quad processors have the following power-up sequence requirements:

• Turn on NVCC_SNVS

• Turn on VDD_SNVS

• RTC_RESET_B release (after 32K clock stable and before POR_B release, no constraint with any other power supplies)

Power-down sequence MIMX8MQ6DVAJZAA

The i.MX 8M Dual / 8M QuadLite / 8M Quad processors have the following power-down sequence requirements:

• Turn off NVCC_SNVS and VDD_SNVS last

• Turn off VDD_SOC after the other power rails or at the same time as other rails

• No sequence for other power rails during power down