NT5CC256M8IN-DI 全新原装 DDR3

NT5CC256M8IN-DI 全新原装 DDR3

JEDEC DDR3 Compliant

-8n Prefetch Architecture

-Differential Clock(CK/CK )and Data Strobe(DQS/DQS)

-Double-data rate on DQs, DQSandDM

Data Integrity

-AutoSelf Refresh (ASR)by DRAM built

-inTS-Auto Refreshand Self Refresh Modes

Power Saving Mode

-Partial Array Self Refresh (PASR)1

-Power Down Mode

Signal Integrity

-Configurable DS for system compatibility

-ConfigurableOn-Die Termination

-ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ±1%)

Signal Synchronization

 -Write Leveling via MR settings6

-Read Leveling via MPR

Interface and Power Supply

-SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)

-SSTL_1353for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V

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