MT41K256M8DA-125:K 全新 LPDDR3 D9PSH

MT41K256M8DA-125:K 全新 LPDDR3 D9PSH

? VDD = VDDQ = 1.35V (1.283–1.45V)

? Backward-compatible to VDD = VDDQ = 1.5V ±0.075V

? Differential bidirectional data strobe

? 8n-bit prefetch architecture

? Differential clock inputs (CK, CK#)

? 8 internal banks

? Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

? Programmable CAS (READ) latency (CL)

? Programmable posted CAS additive latency (AL)

? Programmable CAS (WRITE) latency (CWL)

? Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

? Selectable BC4 or BL8 on-the-fly (OTF)

? Self refresh mode

? TC of 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

? Self refresh temperature (SRT)

? Automatic self refresh (ASR)

? Write leveling

? Multipurpose register

? Output driver calibration

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