MT41K64M16TW-107 IT:J 原装 LPDDR3

MT41K64M16TW-107 IT:J 原装 LPDDR3

动态随机存取存储器 DDR3 1G 64MX16 FBGA

SDRAM - DDR3L 存储器 IC 1Gb（64M x 16） 并联 933 MHz 20 ns 96-FBGA（8x14）

MT41K64M16TW-107 IT:J 原装 LPDDR3 的技术参数：

MT41K64M16TW-107 IT:J 原装 LPDDR3 的描述：

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.

 A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK.