Verilog HDL奇偶电路

　9位奇偶发生器门级模型描述如下：

module Parity_9_Bit (D, Even,Odd);
input [0:8] D;
output Even, Odd;
xor # (5,4)
XE0 (E0,D[0],D[1]),
XE1 (E1,D[2],D[3]),
XE2 (E2,D[4],D[5]),
XE3 (E3,D[6],D[7]),
XF0 (F0,E0,E1),
XF1 (F1,E2,E3),
XH0 (H0,F0,F1),
XEVEN (Even, D[8], H0);
not #2
XODD (Odd, Even);
endmodule