DDR存储器/MT41K512M16HA-125:A

MT41K512M16HA-125:A  MT41K512M16HA-125:A  MT41K512M16HA-125:A  MT41K512M16HA-125:A

Description

DDR3L (1.35V) SDRAM is a low voltage version of the

DDR3 (1.5V) SDRAM. Refer to a DDR3 (1.5V) SDRAM

data sheet specifications when running in 1.5V com-

patible mode.

Features

• V DD = V DDQ = 1.35V (1.283–1.45V)

• Backward compatible to V DD = V DDQ = 1.5V ±0.075V

– Supports DDR3L devices to be backward com-

patible in 1.5V applications

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

• Programmable CAS (READ) latency (CL)

• Programmable posted CAS additive latency (AL)

• Programmable CAS (WRITE) latency (CWL)

• Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

• T C  of 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Write leveling

• Multipurpose register

• Output driver calibration

Options Marking

• Configuration

– 2 Gig x 4 2G4

– 1 Gig x 8 1G8

– 512 Meg x 16 512M16

• FBGA package (Pb-free) – x4, x8

– 78-ball (9mm x 13.2mm) SN

• FBGA package (Pb-free) – x16

– 96-ball (9mm x 14mm) HA

• Timing – cycle time

– 1.25ns @ CL = 11 (DDR3-1600) -125

– 1.07ns @ CL = 13 (DDR3-1866) -107

• Operating temperature

– Commercial (0°C ? T C ? +95°C) None

– Industrial (–40°C ? T C ? +95°C) IT

• Revision :A