ST10F272Z2Q3　16位微控制器

ST10F272Z2Q3 256KBit Flash,20KBit RAM,16位微控制器LQFP-144封装

ST10F272Z2Q3概述

The architecture of the ST10F272Z2 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F272Z2.

The ST10F272Z2 device is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. The ST10F272Z2 combines high CPU performance (up to 32 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides onchip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F272Z2 is processed in 0.18 μm CMOS technology. The MCU core and the logic is supplied with a 5 V to 1.8V on-chip voltage regulator. The part is supplied with a single 5 V supply and I/Os work at 5 V.

The device is upward compatible with the ST10F269 device, with the following set of differences:Flash control interface is now based on STMicroelectronics third generation of stand-alone Flash memories (M29F400 series), with an embedded Program/Erase Controller. This completely frees up the CPU during programming or erasing the Flash.Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package is used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin to 5.0V external supply. Instead, this pin should be connected to a decoupling capacitor (ceramic t*e, t*ical value 10 nF, maximum value 100nF).

The AC and DC parameters are modified due to a difference in the maximum CPU frequency.A new VDD pin replaces DC2 of ST10F269.EA pin *umes a new alternate functionality: it is also used to provide a dedicated power supply (see VSTBY) to maintain biased a portion of the XRAM (16 Kbytes) when the main Power Supply of the device (VDD and consequently the internally generated V18) is turned off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5-5.5 Volt, and a dedicated embedded low power voltage regulator is in charge to provide the 1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator and the Real-Time Clock module when not disabled. It is allowed to exceed the upper limit up to 6V for a very short period of time during the global life of the device, and exceed the lower limit down to 4V when RTC and 32 kHz on-chip oscillator are not used.

A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here SSC0,while the new one is referred as XSSC or simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the cl*ic SSC, and the new XSSC.A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0, while the new one is referred as XASC or simply as ASC1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the cl*ic ASC, and the new XASC. A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here PWM0,while the new one is referred as XPWM or simply as PWM1). Note that some restrictions and functional differences due to the XBUS peculiarities are present between the cl*ic PWM, and the new XPWM.An I²C interface on the XBUS is added (see X-I²C or simply I²C interface).

ST10F272Z2Q3 特性:

• 16-bit CPU with DSP functions
  – 31.25 ns instruction cycle time at 64 MHz max CPU clock
  – Multiply/accumulate unit (MAC) 16 x16-bit multiplication, 40-bit accumulator
  – Enhanced boolean bit manipulations
  – Single-cycle context switching support
• On-chip memories
  – 256 Kbyte Flash memory (32-bit fetch)
  – Single voltage Flash memories with erase/program controller and 100K erasing/programming cycles.
  – Up to 16 Mbyte linear address space for code and data (5 Mbytes with CAN or I²C)
  – 2 Kbyte internal RAM (IRAM)
  – 18 Kbyte extension RAM (XRAM)
  – Programmable external bus configuration& characteristics for different address ranges
  – Five programmable chip-select signals
  – Hold-acknowledge bus arbitration support
• Interrupt
  – 8-channel peripheral event controller for single cycle interrupt driven data transfer
  – 16-priority-level interrupt system with 56 sources, sampling rate down to 15.6ns
• Timers
  – Two multi-functional general purpose timer units with 5 timers
• Two 16-channel capture / compare units
• 4-channel PWM unit + 4-channel XPWM
• A/D converter
  – 24-channel 10-bit
  – 3μs minimum conversion time
• Serial channels
  – Two synch. / asynch. serial channels
  – Two high-speed synchronous channels
  – One I²C standard interface
• 2 CAN 2.0B interfaces operating on 1 or 2 CAN busses (64 or 2x32 message, C-CAN version)
• Fail-safe protection
  – Programmable watchdog timer
  – Oscillator watchdog
• On-chip bootstrap loader
• Clock generation
  – On-chip PLL with 4 to 8 MHz oscillator
  – Direct or prescaled clock input
• Real-time clock and 32 kHz on-chip oscillator
• Up to 111 general purpose I/O lines
  – Individually programmable as input, output or special function
  – Programmable threshold (hysteresis)
• Idle, power down and stand-by modes
• Single voltage supply: 5 V &plu*n;10%

ST10F272Z2Q3 订购型号:

ST10F272Z2Q3 技术支持

1. ST10F272Z2 数据手册 DataSheet 下载.pdf
2. ST10 16位微控制器选型参数
3. 手册和产品指南.pdf
4. 8、16、32位微控制器.pdf
5. 意法半导体应用支持. PDF
6. *半导体解决方案的门电子
7. 电机控制参考指南
8. 周围半导体机顶盒应用. PDF
9. STM32,STR7和STR9开发工具. PDF
10. 8 ,16和32位微控制器产品和工具选择指南. PDF
11. 电机控制选型指南. PDF