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The C6745/6747 is a Low-power applications processor based on C674x™ DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The C6745/6747 enables *s and ODMs to quickly bring to market devices featuring high processing performance.
The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-*ociative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two
TMS320C6745 | |
CPU | 1 C674x |
Frequency (MHz) | 375,456 |
Peak MMACS | 3000,3648 |
On-Chip L1/SRAM | 64 KB |
On-Chip L2/SRAM | 256 KB |
EMIF | 1 8-Bit EMIFA,32/16-Bit EMIFB |
External Memory T*e Supported | Async SRAM,SDRAM,NAND Flash,*R |
DMA (Ch) | 32-Ch EDMA |
EMAC | 10/100 |
HPI | |
LCD | |
MMC/SD | 1 |
I2C | 2 |
SPI | 2 |
UART (SCI) | 3 |
U* | 1 |
PWM (Ch) | 3 |
eCAP | 3 |
McASP | 2 |
Timers | 1 64-Bit GP,1 64-Bit GP/WD |
RTC | |
Core Supply (Volts) | 1.2 V,1.3 V |
IO Supply (V) | 1.8 V,3.3 V |
Operating Temperature Range (C) | -40 to 105,0 to 90,0 to 85 |
tms320c6745
TI
64位