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直接数位合成技术及FPGA晶片设计
频率范围:0.1Hz~7MHz
频率解析度:100mHz
频率准确度及飘移度:+/-20ppm
低失真正弦波:-55dBc,0.1Hz~200kHz
输出波形:正弦波、方波、三角波
具TTL及CMOS OUT
前面板可设定十组储存及呼叫操作记忆
规格
|
MAIN |
Frequency Range
(For Sine, Square) |
0.1Hz~7MHz |
Frequency Range
(For Triangle) |
0.1Hz~1MHz |
| Frequency Resolution |
0.1Hz |
| Frequency Stability |
± 20 ppm |
| Frequency Accuracy |
± 20 ppm |
| Frequency Aging |
± 5 ppm / year |
| Output Function |
Sine, Square, Triangle |
| Amplitude Range |
10Vpp(into 50Ωload) |
| Flatness(Sinewave relative to 1kHz) |
＜± 0.3dB,0.1Hz～1MHz; ＜± 0.5dB,1MHz～4MHz; ＜± 2dB, 4MHz～10MHz |
| Impedance |
50Ω±10％ |
| Attenuator |
-20dB±1dB×2 |
| DC Offset |
＜-5V～＞+5V(into 50Ωload) |
| Duty Control Range |
20% to 80% below 1MHz (Square wave only) |
| Duty Control Resolution |
1% |
| Display |
9 di*s LED display |
|
SINE W*E |
| Harmonics Distortion |
-55dBc,0.1Hz～200kHz; -40dBc,0.2MHz～4MHz; -30dBc,4MHz～10MHz
(Specification applied from MAX. to 1/10 level) |
|
TRIANGLE W*E |
| Linear |
≧98％,0.1Hz～100kHz;≧95％,100kHz～1MHz |
|
SQUARE W*E |
| Symmetry |
± 1% of period +4ns to 0.1Hz～100kHz ;Rise or Fall Time; ≦25ns at maximum output.(into 50Ωload) |
|
CMOS OUTPUT |
| Level |
4Vpp±1Vpp～14.5Vpp±0.5Vpp adjustable; Rise or Fall Time; ≦120ns |
|
TTL OUTPUT |
| Level |
≧3Vpp ; Fan Out; 20 TTL load ; Rise or Fall Time ; ≦25ns |
| STORE/RECALL FUN*ION |
|
10 groups of Setting memories |
| POWER SOURCE |
AC115V, 230V±15%,50/60Hz |
|
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ACC*SORI* |
|
Instruction manual x 1
Power Cord x 1
GTL-101 x 1 |
| DIMENSION & WEIGHT |
107(W)×266(H)×293(D) m/m
Approx. 3.1kg | |
