LMK04208NKDT Texas Instruments 时钟合成器/抖动清除器 Ultra Low Noise Clock Jitter Cleaner With 6

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1 Features

1• Ultra-Low RMS Jitter Performance

– 111 fs, RMS Jitter (12 kHz to 20 MHz)

– 123 fs, RMS Jitter (100 Hz to 20 MHz)

• Dual Loop PLLatinum™ PLL Architecture

• PLL1

– Integrated Low-Noise Crystal Oscillator Circuit

– Holdover Mode when Input Clocks are Lost

– Automatic or Manual Triggering/Recovery

• PLL2

– Normalized PLL Noise Floor of –227 dBc/Hz

– Phase Detector Rate of Up to 155 MHz

– OSCin Frequency-Doubler

– Integrated Low-Noise VCO or External VCO

Mode

2 Applications

• Data Converter Clocking

• Wireless Infrastructure

• Networking, SONET/SDH, DSLAM

• Medical, Video, Military, Aerospace

• Test and Measurement

3 Description

The LMK04208 is a high performance clock

conditioner with superior clock jitter cleaning,

generation, and distribution with advanced features to

meet next generation system requirements. The dual

loop PLLatinum™ architecture is capable of 111 fs,

RMS jitter (12 kHz to 20 MHz) using a low-noise

VCXO module or sub-200 fs rms jitter (12 kHz to 20

MHz) using a low cost external crystal and varactor

diode.

The dual loop architecture consists of two highperformance

phase-locked loops (PLL), a low-noise

crystal oscillator circuit, and a high-performance

voltage controlled oscillator (VCO). The first PLL

(PLL1) provides low-noise jitter cleaner functionality

while the second PLL (PLL2) performs the clock

generation. PLL1 can be configured to either work

with an external VCXO module or the integrated

crystal oscillator with an external tunable crystal and

varactor diode. When paired with a very narrow loop

bandwidth, PLL1 uses the superior close-in phase

noise (offsets below 50 kHz) of the VCXO module or

the tunable crystal to clean the input clock. The

output of PLL1 is used as the clean input reference to

PLL2 where it locks the integrated VCO. The loop

bandwidth of PLL2 can be optimized to clean the farout

phase noise (offsets above 50 kHz) where the

integrated VCO outperforms the VCXO module or

tunable crystal used in PLL1.


输出端数量:

7 Output

输出电平:

LVCMOS, LVDS, LVPECL

输出频率:

3072 MHz

封装 / 箱体:

WQFN-64