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1 Features
1• Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: -40℃ to +105℃
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8kV
– Device CDM ESD Classification Level C6
• 25-MHz to 100-MHz Input Pixel Clock Support
• Programmable Data Payload:
– 10-bit Payload up to 100 MHz
– 12-bit Payload up to 75 MHz
• Continuous Low Latency Bidirectional Control
Interface Channel with I2C Support @400 kHz
• Embedded Clock with DC-Balanced Coding to
Support AC-Coupled Interconnects
• Capable of Driving up to 15m Coaxial or 20m
Shielded Twisted-Pair Cables
• Robust Power-Over-Coaxial (PoC) Operation
• 4 Dedicated General Purpose Input/Output
• 1.8-V, 2.8-V or 3.3-V-Compatible Parallel Inputs
on Serializer
• Single Power Supply at 1.8 V
• ISO 10605 and IEC 61000-4-2 ESD Compliant
• Small Serializer Footprint (5 mm x 5 mm)
2 Applications
• Automotive
– Surround View Systems (SVS)
– Rear and Front View Cameras
– Driver Monitor Cameras (DMS)
– Remote Satellite RADAR Sensors
• Security and Surveillance
• Industrial Machine Vision
3 Description
The DS90UB913A-Q1 device offers an FPD-Link III
interface with a high-speed forward channel and a
bidirectional control channel for data transmission
over a single coaxial cable or differential pair. The
DS90UB913A-Q1 device incorporates differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
serializer/deserializer pair is targeted for connections
between imagers and video processors in an ECU
(Electronic Control Unit). This device is ideally suited
for driving video data requiring up to 12-bit pixel
depth plus two synchronization signals along with
bidirectional control channel bus.
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical-bidirectional
control channel information. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins. Internal DC-balanced
encoding/decod
1.8 V
- 40 C
+ 105 C
WQFN-32
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