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具有闪存的 32 位数字信号控制器
High-Performance Static CMOS Technology – 150 MHz (6.67-ns Cycle Time) – Low-Power (1.8-V Core, 3.3-V I/O) Design – 3.3-V Flash Programming Voltage High-Performance CPU (C28x) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – 4M Linear Program Address Reach – 4G Linear Data Address Reach – Code-Efficient (in C/C++ and Assembly) – TMS320F24x/LF240x Processor Source Code Compatible On-Chip Memory – Up to 128K x 16 Flash (8 x 4K and 6 x 16K Sectors) – 2K x 16 OTP ROM – L0 and L1: 2 Blocks of 4K x 16 Single-Access RAM (SARAM) – H0: 1 Block of 8K x 16 SARAM – M0 and M1: 2 Blocks of 1K x 16 SARAM Boot ROM (4K x 16) – With Software Boot Modes – Standard Math Tables External Interface (F2812) – Up to 1.5M Total Memory – Programmable Wait States – Programmable Read/Write Strobe Timing – Four Individual Chip SelectsClock and System Control – Dynamic PLL Ratio Changes Supported – On-Chip Oscillator – Watchdog Timer Module Three External Interrupts Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts
TMS320F2812PGFS
TI
BGA
20+
TMS320F2812PGFS
TI
信号控制器