The on-chip rate converter supports a wide range of baud rates
with a fixed DAC clock. The digital upconverter can place the
channels from 0 to 0.5 × fDAC. This permits four contiguous
channels to be synthesized and placed anywhere from dc to fDAC/2.
The AD9789 includes a serial peripheral interface (SPI) for
device configuration and status register readback. The flexible
digital interface can be configured for data bus widths of 4, 8,
16, and 32 bits. It can accept real or complex data.
The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for
a total power consumption of 1.6 W. It is supplied in a 164-ball
chip scale package ball grid array for lower thermal impedance
and reduced package parasitics. No special power sequencing
is required. The clock receiver powers up muted to prevent
start-up noise.
