供应GL3510-USB 3.1 Gen 1集线器控制器

GL3510 电子元器件 GENESYS/创惟科技 封装QFN-48 USB 3.1 Gen 1集线器控制器

DESCRIPTION
Genesys GL3510 is a 4-port/2-port, low-power, and configurable hub controller. It is compliant with the USB 3.1 specification. GL3510 integrates Genesys Logic self-developed USB 3.1 Gen 1 Super Speed transmitter/receiver physical layer (PHY) and USB 2.0 High-Speed PHY. It supports Super Speed, Hi-Speed, and Full-Speed USB connections and is fully backward compatible to all USB 2.0 and USB 1.1 hosts. GL3510 has built-in 5V to 3.3V and 5V to 1.2V regulators, which saves customers’ BOM cost, and eases for PCB design.
GL3510 features the native fast-charging and complies with USB-IF battery charging specification rev1.2, it could fast-charge Apple, Samsung Galaxy devices, and any device complaint with BC1.2/1.1. It also allows portable devices to draw up to 1.5A from GL3510 charging downstream ports (CDP1) or dedicated charging port (DCP2). It can enable systems to fast charge handheld devices even during “Sleep” and “Power-off” modes.

FEATURES
Compliant with USB 3.1 Gen 1 Specification
Upstream port supports SuperSpeed (SS), HighSpeed (HS) and FullSpeed (FS) trfic
Downstream ports support SS, HS, FS, and LowSpeed (LS) trafic
1 control pipe and 1 interupt pipe
Backward compatible to USB specification Revision 2.0/1.1
Featuring fast-charging on all downstream ports and upstream port
Compliant with USB Battery Charging Revision v1.2, supporting CDP, DCP, and ACA-Dock
Downstream ports can be turned from a Standard Downstream Port (SDP) into Charging Downstream
Port (CDP) or Dedicated Charging Port (DCP)
Downstream devices can be charged while upstream VBUS is not present, which can be applied on wall
charger applications
Upstream port is capable of charging and data communicating simultaneously for portable devices
supporting ACA-Dock or proprietary charging protocols
Supporting Apple 1A/2.1A/2.4A and Samsung Galaxy devices fast-charging
)On-chip 8-bit micro-processor
RISC-like architecture
USB optimized instnuction set
1 cycle instnuction execution (maximum)
Performance: 12 MIPS @ 12.5MHz (maximum)
With 256-byte RAM, 20K-byte intermnal ROM, and 24K-byte SRAM
Single Transaction Translator (TT) architecture
Advanced power management and low power consumption
- Supporting USB 3.1 U0/U1/U2/U3 power management states
Supporting USB Link Power Management (LPM) L0/L1/L2 .
Supporting low active power switch
Configurable settings
- Configurable charging port
Supporting compound-device (non-removable setting on downstream ports)
Flexible design
-Supporting Poly- fuse/Power-switch
Automatic switching between self- powered and bus powered modes
Supporting electrical tuning for each specific port
Allow downstream ports to connect up to 8 devices, 4 x USB3.1 non-removable devices with 4 x
USB2.0 non-removable devices or exposed ports
Low BOM cost
-Single external 25 MHz crystal / Oscillator clock input
Built-in upstream port 1.5K2 pull-up and downstream port 15K2 pull-down resistors
Built-in5 to 3.3V and5 to 1.2V regulator
Applications
Standalone USB hub/Docking station
USB wall charger