The 512Mb SDRAM is a high speed CMOS, dynamic
random-accessmemorydesignedtooperateineither3.3V
Vdd/Vddq or 2.5V Vdd/Vddq memory systems, depending
on the DRAM option. Internally configured as a quad-bank
DRAM with a synchronous interface.
The 512Mb SDRAM (536,870,912 bits) includes an AUTO
REFRESH MODE, and a power-saving, power-down
mode. All signals are registered on the positive edge of
the clock signal, CLK. All inputs and outputs are LVTTL
compatible.
The 512Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
