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0 Certified to MIL-PRF-38535 (Qualified Manufacturer Listing)
0 100% factory tested
0 Guaranteed over the full military temperature range (–55°C to +125°C) or industrial temperature range (–40°C to +100°C)
0 Ceramic and plastic wire-bond and flip-chip grid array packages
0 IP-immersion architecture
♦ Densities from 1M to 6M system gates
♦ 300+ MHz internal clock speed (Advance Data) ♦ 622+ Mb/s I/O (Advance Data)
0 SelectRAM™ Memory Hierarchy
♦ 2.5 Mb of dual-port RAM in 18 Kbit block SelectRAM resources
♦ Up to 1 Mb of distributed SelectRAM resources
0 High-performance interfaces to external memory ♦ DRAM interfaces
0 SDR/DDR SDRAM
0 Network FCRAM
0 Reduced Latency DRAM ♦ SRAM interfaces
0 SDR/DDR SRAM
0 QDR SRAM ♦ CAM interfaces
0 Arithmetic functions
♦ Dedicated 18-bit x 18-bit multiplier blocks ♦ Fast look-ahead carry logic chains
0 Flexible logic resources
0 Up to 67,584 internal registers/latches with Clock Enable
0 Up to 67,584 look-up tables (LUTs) or cascadable 16-bit shift registers
0 Wide multiplexers and wide-input function support
0 Horizontal cascade chain and sum-of-products support
0 Internal 3-state busing
igital Clock Manager) modules
0 Precise clock de-skew
0 Flexible frequency synthesis
0 High-resolution phase shifting ♦ 16 global clock multiplexer buffers
0 Active interconnect technology
♦ Fourth-generation segmented routing structure
♦ Predictable, fast routing delay, independent of fanout
0 SelectIO™-Ultra Technology ♦ Up to 824 user I/Os
♦ 19 single-ended and six differential standards
♦ Programmable sink current (2 mA to 24 mA) per I/O
♦ Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards
♦ PCI compliant (32/33 MHz) at 3.3V ♦ Differential signaling
♦ 622 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers
♦ Bus LVDS I/O
♦ Lightning Data Transport (LDT) I/O with current driver buffers
♦ Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O
♦ Built-in DDR input and output registers
♦ Proprietary high-performance SelectLink Technology
0 High-bandwidth data path
0 Double Data Rate (DDR) link
0 Web-based HDL generation methodology
0 Supported by Xilinx Foundation Series™ and Alliance Series™ Development Systems
♦ Integrated VHDL and Verilog design flows ♦ Compilation of 10M system gates designs ♦ Internet Team Design (ITD) tool
• SRAM-based in-system configuration
♦
Unlimited reprogrammability
♦
Fast SelectMAP configuration
♦
Readback capability
♦ Triple Data Encryption Standard (DES) security
• 0.15 μm 8-layer metal process with 0.12 μm high-
option (Bitstream Encryption)
speed transistors
♦
IEEE 1532 support
• 1.5V (VCCINT) core power supply, dedicated 3.3V
♦
Partial reconfiguration
VCCAUX auxiliary and VCCO I/O power supplies
XQ2V3000-4CG717M
XILINX
BGA
15+