NT5CC128M16JR-EK 全新原装 DDR3

NT5CC128M16JR-EK 全新原装 DDR3

Commercial and Industrial DDR3(L) 2Gb SDRAM

NT5CC128M16JR-EK 全新原装 DDR3 的技术参数：

Basis DDR3 Compliant

- 8n Prefetch Architecture

- Differential Clock(CK/CK) and Data Strobe(DQS/DQS)

- Double-data rate on DQs, DQS and DM

Data Integrity

- Auto Self Refresh (ASR) by DRAM built-in TS

- Auto Refresh and Self Refresh Modes

Power Saving Mode

- Power Down Mode

Signal Integrity

- Configurable DS for system compatibility

- Configurable On-Die Termination

- ZQ Calibration for DS/ODT impedance accuracy viaexternal ZQ pad (240 ohm ± 1%)

Signal Synchronization

- Write Leveling via MR settings 5

- Read Leveling via MPR

Interface and Power Supply

- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)

- SSTL_1353for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)