供应MT29F256G08CJABB 原装 NAND Flash

MT29F256G08CJABB 原装 NAND Flash

 IC FLASH 256G PARALLEL 48TSOP

Features

• Open NAND Flash Interface (ONFI) 2.3-compliant1

• JEDEC NAND Flash Interface Interoperability

(JESD230) compliant

• Multiple-level cell (MLC) technology

• Organization

– Page size x8: 8936 bytes (8192 + 744 bytes)

– Block size: 256 pages (2048K + 186K bytes)

– Plane size: 2 planes x 2048 blocks per plane

– Device size: 64Gb: 4096 blocks;

128Gb: 8192 blocks;

256Gb: 16,384 blocks

• Synchronous I/O performance

– Up to synchronous timing mode 52

– Clock rate: 10ns (DDR)

– Read/write throughput per pin: 200MT/s

• Asynchronous I/O performance

– Up to asynchronous timing mode 5

– tRC/tWC: 20ns (MIN)

– Read/write throughput per pin: 50MT/s

• Array performance

– Read page: 100μs (MAX)

– Program page: 1300μs (TYP)

– Erase block: 3ms (TYP)

• Operating Voltage Range

– VCC: 2.7–3.6V

– VCCQ: 1.7–1.95V, 2.7–3.6V

• Command set: ONFI NAND Flash Protocol

• Advanced Command Set

– Program cache

– Read cache sequential

– Read cache random

– One-time programmable (OTP) mode

– Multi-plane commands

– Multi-LUN operations

– Read unique ID

– Copyback

– Read Retry

• First block (block address 00h) is valid when shipped from factory. For minimum required ECC, see

Error Management (page 119).3

 

• RESET (FFh) required as first command after power-on

• Operation status byte provides software method for

detecting

– Operation completion

– Pass/fail condition

– Write-protect status

• Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the synchronous

interface

• Copyback operations supported within the plane

from which data is read

• Quality and reliability3

– Data retention: JESD47 compliant; see qualification report

– Endurance: 3000 PROGRAM/ERASE cycles

• Operating temperature:

– Commercial: 0°C to +70°C

– Industrial (IT): –40oC to +85oC

• Package

– 48-pin TSOP

– 100-ball BGA

2. BGA devices up to Synchronous timing

mode 5. TSOP devices up to Synchronous

timing mode 4.

3. Read Retry operations are required to achieve specified endurance and for general array data integrity

 

 

Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer

commands, address, and data. There are five control signals used to implement the

asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control

hardware write protection (WP#) and monitor device status (R/B#).