供应TPS51206DSQT 原装 PMIC

TPS51206DSQT 原装 PMIC 

TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4

TPS51206DSQT 原装 PMIC 的技术参数：

TPS51206DSQT 原装 PMIC 的描述：

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration.

The device maintains fast transient response and only requires 1×10-μF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

The TPS51206 device is available in 10-Pin, 2 mm×2 mm SON (DSQ) PowerPAD™package and specified from–40°C to 105°C.