图文详情
产品属性
相关推荐
Hi3518E V200 Economical HD IP Camera SoC
Brief Data Sheet
Issue 02 (2015-12-28) HiSilicon Proprietary and Confidential
Copyright © HiSilicon Technologies Co., Ltd 3
Key Specifications
Processor Core
ARM926@540 MHz, 32 KB I-cache, 32 KB D-cache
Video Encoding
H.264 main/high profile L4.0
H.264 baseline encoding
MJPEG/JPEG baseline encoding
Video Encoding Performance
A maximum of 2-megapixel resolution for H.264
encoding
Real-time H.264 & JPEG encoding of multiple streams:
720p@30 fps+VGA@30 fps+QVGA@30 fps+720p@1
fps JPEG snapshot
2 megapixels@5 fps JPEG snapshot
CBR or VBR with the output bit rate ranging from 2 kbit/s
to 100 Mbit/s
Encoding frame rate ranging from 1/16 fps to 30 fps
Encoding of eight ROIs
OSD overlaying of eight regions before encoding
Intelligent Video Analysis
Integrated IVE, supporting various intelligent analysis
applications such as motion detection, perimeter defense,
and video diagnosis
Video and Graphics Processing
Video pre-processing, including 3D denoising, image
enhancement, and edge enhancement
Anti-flicker for output videos and graphics
1/15x to 16x video scaling
1/2x to 2x graphics scaling
OSD overlaying of eight regions before encoding
Hardware graphics overlaying for videos at the video layer
and graphics layer 1 during post-processing
ISP
2x2 Pattern RGB-IR sensor
Adjustable 3A (AE, AF, and AWB) functions
Highlight compensation, backlight compensation, gamma
correction, and color enhancement
Defect pixel correction, denoising, and digital image
stabilization
Anti-fog
Lens distortion correction
Picture rotation by 90° or 270°
Mirroring and flipping
Build-in WDR and tone mapping
ISP tuning tools for the PC
Audio Encoding/Decoding
Voice encoding/decoding complying with multiple
protocols by using software
G.711, ADPCM, and G.726 protocols supported
Echo cancellation, noise suppression, and automatic gain
Security Engine
AES, DES, 3DES, and RSA encryption/decryption
algorithms implemented by hardware
Hash digest tamper proofing implemented by hardware
Integrated 512-bit OTP storage space and hardware
random number generator
Video Interfaces
VI interfaces
− 8-, 10-, 12-, or 14-bit RGB Bayer/RGB-IR inputs,
maximum clock frequency of 100 MHz
− BT.601, BT.656, and BT.1120 VI interfaces
− 4-Lane MIPI/HiSPI/LVDS VI interfaces
− Compatibility with mainstream HD CMOS sensors
provided by Sony, Aptina, OmniVision, and Panasonic
− Various sensor levels supported
− Programmable sensor clock output
− Maximum input resolution of 2 (1920*1080)
megapixels
VO interfaces
− One BT.656 VO interface supporting 8-bit serial LCD
outputs
Audio Interfaces
Integrated audio CODEC that supports 16-bit audio inputs
and outputs
Mono-channel differential microphone inputs for reducing
the background noises
I2S input
Peripheral Interfaces
POR
One integrated high-precision RTC
One 4-channel SAR ADC
Three UART interfaces
IR interfaces, I2C interfaces, SPI master interfaces, and
GPIO interfaces
Four PWM interfaces
Two SDIO interfaces, one of which supports SD 3.0
One USB 2.0 interface that supports the host/device mode
RMII in 10/100 Mbit/s full-duplex or half-duplex mode,
TSO network acceleration, and PHY clock output
External Memory Interfaces
DDR2 SDRAM interface
− Embedded 512 Mbits, 16-bit DDR2 SDRAM
− Maximum frequency of 360 MHz
SPI NOR flash interface
− 1-, 2-, or 4-bit SPI NOR flash interface
SPI NAND flash interface
− Maximum capacity of 4 Gbits
eMMC 5.0 interface
− Maximum capacity of 64 GB
Booting from the SPI NOR flash, SPI NAND flash, or
eMMC
ARM926@540 MHz, 32 KB I-cache, 32 KB D-cache
DDR2 SDRAM interface − Embedded 512 Mbits, 16-bit DDR2 SDRAM − Maximum frequency
2x2 Pattern RGB-IR sensor
Video pre-processing, including 3D denoising, image enhancement, and edge enhanc