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? Instructions With Two- or Three-Operand
Arithmetic Instructions With Parallel Store
and Parallel Load
? Conditional Store Instructions
? Fast Return From Interrupt
? On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable Bank
Switching
– On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Enhanced 8-Bit Parallel Host-Port
Interface (HPI8)
– Two 16-Bit Timers
– Six-Channel Direct Memory Access
(DMA) Controller
? Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
? CLKOUT Off Control to Disable CLKOUT
? On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1 † (JTAG) Boundary Scan
Logic
? 10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS) for 3.3-V Power
Supply (1.8-V Core)
? Available in a 144-Pin Plastic Low-Profile
Quad Flatpack (LQFP) (PGE Suffix) and a
144-Pin Ball Grid Array (BGA) (GGU Suffix)
TMS320VC5402PGE100
TI
TQFP144
盘装