FE1.1s USB-HUB扩展芯片

FE1.1s INTRODUCTION

The FE1.1s is a highly integrated, high quality, high performance, low power consumption, yet low cost solution for USB 2.0 High Speed 4-Port Hub. It adopts Single Transaction Translator (STT) architecture to be more cost effective. Six, instead of two, non-periodic transaction buffers are used to minimize potential traffic jamming. The whole design is based on state-machine-control to reduce the response delay time; no micro controller is used in this chip.

FE1.1s FEATURES

* Low power consumption

- 100 mA when four Downstream ports enabled in High-Speed mode;

- 57 mA when one Downstream port enabled in High-Speed mode;

* Fully compliant with Universal Serial Bus Specification Revision 2.0 (USB 2.0);

- Upstream facing port supports High-Speed (480MHz) and Full-Speed (12MHz) modes;

- 4 downstream facing ports support High-Speed (480MHz), Full-Speed (12MHz), and Low-Speed (1.5MHz)

modes;