1 Features
1
•
–40°C to +125°C Ambient Operating Temperature
Range
•
An AEC-Q100 Qualified Device is Available
•
VIN 3.8 V to 45 V (47 V Absolute Maximum)
•
Output: Fixed 3.3 V, 5 V, or Adjustable From
1.5 V - 15 V with ±0.8% Accuracy
•
Fixed 2.2 MHz or 440 kHz Switching Frequency
with ±5% Accuracy
•
High-Side and Low-Side Gate Drive With Slew
Rate Control
•
Optional Frequency Shift by Varying an Analog
Voltage or RT Resistor
•
Optional Synchronization to an External Clock
•
Optional Spread Spectrum
•
Shutdown Mode IQ: 10 μA Typical
•
Low Standby Mode IQ: 35 μA Typical
•
75 mV Current Limit Threshold with ±0.9%
Accuracy
•
External Resistor or DCR Current Sensing
•
Output Enable Logic Input
•
Hiccup Mode for Sustained Overload
•
Power Good Indication Output
•
Selectable Diode Emulation or Forced Pulse
Width Modulation
•
QFN-24 Package with Wettable Flanks
•
Create a Custom Design Using the LM25141 With
the WEBENCH® Power Designer
2 Applications
•
Medical Equipment
•
Industrial Programmable Logic Controller
•
Industrial PC
•
Embedded PC
3 Description
The LM25141 is a synchronous buck controller,
intended
for
high
voltage
wide
VIN
step-down
converter applications. The control method is peak
current mode control. Current mode control provides
inherent line feed-forward, cycle-by-cycle current
limiting,
and
ease
of
loop
compensation.
The
LM25141 features slew rate control to simplify the
compliance with EMI requirements.
The
LM25141
has
two
selectable
switching
frequencies: 2.2 MHz and 440 kHz. Gate Drivers with
slew rate control that can be adjusted to reduce EMI.
In light or no-load conditions, the LM25141 operates
in skip cycle mode for improved low power efficiency.
The LM25141 has a high voltage bias regulator with
automatic switch-over to an external bias to reduce
the IQ
current from VIN. Additional features include
frequency
synchronization,
cycle-by-cycle
current
limit, hiccup mode fault protection for sustained
overload, and power good output.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LM25141
QFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic2
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Table of Contents
1
Features.................................................................. 1
2
Applications ........................................................... 1
3
Description ............................................................. 1
4
Revision History..................................................... 2
5
Pin Configuration and Functions......................... 3
6
Specifications......................................................... 4
6.1
Absolute Maximum Ratings ...................................... 4
6.2
ESD Ratings.............................................................. 5
6.3
Recommended Operating Conditions....................... 5
6.4
Thermal Information.................................................. 5
6.5
Electrical Characteristics........................................... 6
6.6
Switching Characteristics .......................................... 8
6.7
Typical Characteristics .............................................. 9
7
Detailed Description ............................................ 12
7.1
Overview ................................................................. 12
7.2
Functional Block Diagram ....................................... 12
7.3
Feature Description................................................. 13
8
Application and Implementation ........................ 22
8.1
Application Information............................................ 22
8.2
Typical Application ................................................. 22
9
Power Supply Recommendations...................... 35
10 Layout................................................................... 35
10.1
Layout Guidelines ................................................. 35
10.2
Layout Examples................................................... 36
11 Device and Documentation Support ................. 39
11.1
Custom Design With WEBENCH® Tools ............. 39
11.2
Receiving Notification of Documentation Updates 39
11.3
Community Resources.......................................... 39
11.4
Trademarks ........................................................... 39
11.5
Electrostatic Discharge Caution............................ 39
11.6
Glossary ................................................................ 39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
March 2017
*
Initial releaseNot to scale
Thermal
Pad
24 RES
7
LOL
DEMB
1
18 CS
23 EN
8
LO
VDDA
2
17 VOUT
22 SS
9
PGND
AGND
3
16 VCCX
21 PG
10
VCC
RT
4
15 VIN
20 COMP
11
HB
DITH
5
14 HOL
19 FB
12
SW
OSC
6
13 HO
3
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5 Pin Configuration and Functions
RGE Package
24-Pin QFN With Exposed Thermal Pad
Top View
Connect Exposed Pad on bottom to AGND and PGND on the PCB.
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
DEMB
I
Diode Emulation pin. Connect the DEMB pin to AGND to enable diode emulation. If it is
connected to VDDA the LM5141 operates in Forced PWM (FPWM) mode with continuous
conduction at light loads. The DEMB pin can also be used as a synchronization input, to
synchronize the internal oscillator to an external clock.
2
VDDA
P
Internal analog bias regulator output. Connect a capacitor from the VDDA pin to AGND.
3
AGND
G
Analog ground connection. Ground return for the internal voltage reference and analog
circuits.
4
RT
I
A resistor from the RT pin to ground shifts the oscillator frequency up or down from 2.2 MHz
(1.8 MHz to 2.53 MHz), or 440 kHz (300 kHz to 500 kHz). An analog voltage can be applied
to the RT pin (through a resistor) to shift the oscillator frequency.
5
DITH
O
A capacitor connected between the DITH pin and AGND is charged and discharged with a
20 μA current source. If Dither is enabled, the voltage on the DITH pin ramps up and down
modulating the oscillator frequency between –5% and +5% of the internal oscillator.
Connecting DITH to VDDA will disable the dithering feature. DITH is ignored if an external
synchronization clock is used.
6
OSC
I
Frequency selection pin. Connecting the OSC pin to VDDA sets the oscillator frequency to
2.2 MHz. Connecting the OSC pin to AGND sets the frequency to 440 kHz.
7
LOL
O
Low-side gate driver turn-off output.
8
LO
O
Low-side gate driver turn-on output.
9
PGND
G
Power ground connection pin for low-side NMOS gate driver.
10
VCC
P
VCC bias supply pin. Connect a capacitor from the VCC pin to PGND.
11
HB
P
High-side driver supply for bootstrap gate drive.
12
SW
Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal
of the high-side MOSFET and the drain terminal of the low-side MOSFET.
13
HO
O
High-side gate driver turn-on output.
14
HOL
O
High-side gate driver turn-off output.4
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
NAME
15
VIN
P
Supply voltage input source for the VCC regulator
16
VCCX
P
Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to
the VCC pin and the internal VCC regulator is disabled. If VCCX is unused, it should be
grounded.
17
VOUT
I
Current sense amplifier input. Connect this pin to the output side of the current sense
resistor.
18
CS
I
Current sense amplifier input. Make a low current Kelvin connection between this pin and the
inductor side of the external current sense resistor.
19
FB
I
Connect the FB pin to VDDA for a fixed 3.3-V output or connect FB to AGND for a fixed 5-V
output. Connecting the FB pin to the appropriate output divider network will set the output
voltage between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V.
20
COMP
I
Output of the transconductance error amplifier.
21
PG
O
An open collector output which switches low if VOUT is outside of the power good window.
22
SS
I
Soft-start programming pin. An external capacitor and an internal 20-μA current source set
the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below
80 mV turns-off the gate driver outputs, but all the other functions remain active.
23
EN
I
An active high logic input enables the controller.
24
RES
O
Restart timer pin. An external capacitor configures the hiccup mode current limiting. The
capacitor at the RES pin determines the time the controller will remain off before
automatically restarting in hiccup mode. The hiccup mode commences when the controller
experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connecting
the RES pin to VDD during power up disables hiccup mode protection.
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input voltage
VIN
–0.3
47
V
SW to PGND
–0.3
47
V
SW to PGND (20 ns transient)
–5
V
HB to SW
–0.3
6.5
V
HB to SW (20 ns transient)
–5
V
HO, HOL to SW
–0.3
HB + 0.3
V
HO, HOL to SW (20 ns transient)
–5
V
LO, LOL to PGND
–0.3
VCC + 0.3
V
LO, LOL to PGND (20 ns transient)
–1.5
V
OSC, SS, COMP, RES, DEMB, RT, DITH
–0.3
VDD + 0.3
V
EN to PGND
–0.3
47
V
VCC, VCCX, VDD, PG, FB
–0.3
6.5
V
VOUT, CS
–0.3
15.5
V
PGND to AGND
–0.3
0.3
V
Operating junction temperature(2)
–40
150
°C
Storage temperature, Tstg
–65
150
°C5
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(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-
V
C101(2)
±500
(1)
Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(2)
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
VIN
Input voltage
VIN
3.8
42
V
SW to PGND
–0.3
42
V
HB to SW
–0.3
5
5.25
V
HO, HOL to SW
–0.3
HB + 0.3
V
LO, LOL to PGND
–0.3
5
5.25
V
FB, PG, OSC, SS, RES, DEMB,
VCCX
–0.3
5
V
EN to PGND
–0.3
42
V
VCC, VDD
–0.3
5
5.25
V
VOUT, CS
1.5
5
15
V
PGND to AGND
–0.3
0.3
V
Operating junction temperature(2)
–40
125
°C
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1)
LM5141
RGE (QFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
34.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
36.8
°C/W
RθJB
Junction-to-board thermal resistance
12.1
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
12.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.9
°C/W6
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(1)
All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
(2)
The junction temperature (TJ in oC) is calculated from the ambient temperature (TA in oC) and power dissipation (PD in Watts) as follows:
TJ = TA + (PD × RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.
6.5 Electrical Characteristics
TJ = –40°C to +125°C, Typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2
MHz, no-load on the Drive Outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless
otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN SUPPLY VOLTAGE
ISHUTDOWN
Shutdown mode current
VIN = 8–18 V, EN = 0 V, VCCX = 0 V
10
12.5
μA
ISTANDBY
Standby current
EN = 5 V, FB = VDD, VOUT in
regulation, no-load, not switching,
DEMB = GND.
35
45
μA
EN = 5 V, FB = 0 V, VOUT in
regulation, no-load, not switching,
VCCX = 5 V, DEMB = GND.
42
55
VCC REGULATOR
VCC(REG)
VCC regulation voltage
VIN = 6–18 V, 0–75 mA, VCCX = 0 V
4.75
5
5.25
V
VCC(UVLO)
VCC under voltage threshold
VCC rising, VCCX = 0 V
3.25
3.4
3.55
V
VCC(HYST)
VCC hysteresis voltage
VCCX = 0 V
175
mV
ICC(LIM)
VCC sourcing current limit
VCCX = 0 V
85
125
mA
VDDA
VDDA(REG)
Internal bias supply power
VCCX = 0 V
4.75
5
5.25
V
VDDA(UVLO)
VCC rising, VCCX = 0 V
3.1
3.2
3.3
V
VDDA(HYST)
VCCX = 0 V
125
mV
RVDDA
VCCX = 0 V
55
Ω
VCCX
VCCX(ON)
VCC rising
4.1
4.3
4.4
V
VCCX(HYST)
80
mV
R(VCCX)
VCCX = 5 V
2
Ω
OSCILLATOR SELECT THRESHOLDS
Oscillator select threshold 2.2 MHz
(OSC pin)
2.0
V
Oscillator select threshold 440 kHz
(OSC pin)
0.8
V
CURENT LIMIT
V(CS)
Current limit threshold
ILSET = VDDA, measure from CS to
VOUT
68
75
82
mV
tdly
Current sense delay to output
40
ns
Current sense amplifier gain
11.4
12
12.6
V/V
ICS(BIAS)
Amplifier input bias
10
nA
RES
I(RES)
RES current source
20
μA
V(RES)
RES threshold
1.2
V
Timer
Timer hiccup mode fault
512
cycles
RDS(ON)
RES pull-down
4
Ω
OUTPUT VOLTAGE REGULATION
3.3 V
VIN = 3.8–42 V
3.273
3.3
3.327
V
5 V
VIN = 5.5–42 V
4.96
5.0
5.04
V
FEEDBACK
VOUT select threshold 3.3 V
VDD - 0.3
V
Regulated feedback voltage
1.193
1.2
1.207
V
FB(LOWRES)
Resistance to ground on FB for FB
= 0 detection
500
Ω7
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Electrical Characteristics (continued)
TJ = –40°C to +125°C, Typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2
MHz, no-load on the Drive Outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless
otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FB(EXTRES)
Thevenin equivalent resistance at
FB for external regulation detection
FB < 2 V
5
kΩ
TRANSCONDUCTANCE AMPLIFIER
Gm
Gain
Feedback to COMP
1010
1200
μS
Input bias current
15
nA
Transconductance Amplifier source
current
COMP = 1 V, FB = 1 V
100
μA
Transconductance Amplifier sink
current
COMP = 1 V, FB = 1.4 V
100
μA
POWER GOOD
PG(UV)
PG under voltage trip levels
Falling with respect to the regulation
voltage
90%
92%
94%
PG(OVP)
PG over voltage trip levels
Rising with respect to the regulation
voltage
108%
110%
112%
PG(HYST)
3.4%
PG(VOL)
PG
Open collector, Isink = 2 mA
0.4
V
PG(rdly)
OV filter time
VOUT rising
25
μs
PG(fdly)
UV filter time
VOUT falling
30
μs
HO GATE DRIVER
VOLH
HO Low-state output voltage
IHO = 100 mA
0.05
V
VOHH
HO High-state output voltage
IHO = –100 mA, VOHH = VHB - VHO
0.07
V
trHO
HO rise time (10% to 90%)
CLOAD = 2700 pf
4
ns
tfHO
HO fall time (90% to 10%)
CLOAD = 2700 pf
3
ns
IOHH
HO peak source current
VHO = 0 V, SW = 0 V, HB = 5 V,
VCCX = 5 V
3.25
Apk
IOLH
HO peak sink current
VCCX = 5 V
4.25
Apk
V(BOOT)
UVLO
HO falling
2.5
V
Hysteresis
110
mV
I(BOOT)
Quiescent current
3
μA
LO GATE DRIVER
VOLL
LO Low-state output voltage
ILO = 100 mA
0.05
V
VOHL
LO High-state output voltage
ILO = –100 mA, VOHL = VCC - VLO
0.07
V
trLO
LO rise time (10% to 90%)
CLOAD = 2700 pf
4
ns
tfLO
LO fall time (90% to 10%)
CLOAD = 2700 pf
3
ns
IOHL
LO peak source current
VCCX = 5 V
3.25
Apk
IOLL
LO peak sink current
VCCX = 5 V
4.25
Apk
ADAPTIVE DEAD TIME CONTROL
V(GS-DET)
VGS detection threshold
VGS falling, no-load
2.5
V
tdly1
HO off to LO on dead time
20
40
ns
tdly2
LO off to HO on dead time
20
38
ns
DIODE EMULATION
VIL
DEMB input low threshold
0.8
V
VIH
FPWM input high threshold
2.0
V
SW
Zero cross threshold
–5
mV8
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Electrical Characteristics (continued)
TJ = –40°C to +125°C, Typical values TJ = 25°C, VIN = 12 V, VCCX = 5 V, VOUT = 5 V, EN = 5 V, OSC = VDD, FSW = 2.2
MHz, no-load on the Drive Outputs (HO, HOL, LO, and LOL outputs), over operating free-air temperature range (unless
otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE INPUT
VIL
Enable input low threshold
VCCX = 0 V
0.8
V
VIH
Enable input high threshold
VCCX = 0 V
2.0
V
IIkg
Leakage
EN logic input only
1
μA
SYN INPUT (DEMB pin)
VIL
DEMB input low threshold
0.8
V
VIH
DEMB input high threshold
2.0
V
DEMB input low frequency range
440 kHz
350
550
kHz
DEMB input high frequency range
2.2 MHz
1800
2600
kHz
DITHER
IDITHER
Dither source/sink current
20
μA
VDITHER
Dither high threshold
1.26
V
Dither low threshold
1.14
V
SOFT-START
ISS
Soft-Start current
16
22
28
μA
RDS(ON)
Soft-Start pull-down resistance
3
Ω
THERMAL
TSD Thermal Shutdown
175
oC
Thermal shutdown hysteresis
15
oC
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Oscillator Frequency 2.2 MHz
OSC = VDDA, VIN = 8–18 V
2100
2200
2300
kHz
Oscillator Frequency 440 kHz
OSC = GND, VIN = 8–18 V
420
440
460
kHz
RT
Adjustment
Range
Minimum
OSC = VDD, RTMIN = 61.9 kΩ
1710
1800
1890
kHz
Typical
OSC = VDD, RTTYP = 49.9 kΩ
2100
2200
2300
kHz
2.2 MHz
Maximum
OSC = VDD, RTMAX = 43.2 kΩ
2405
2530
2655
kHz
RT
Adjustment
Range
Minimum
OSC = GND, RTMIN = 73.2 k
285
300
315
kHz
Typical
OSC = GND, RTTYP = 49.9 kΩ
420
440
460
kHz
440 kHz
Maximum
OSC = GND, RTMAX = 44.2 kΩ
475
500
525
kHz
RT
Response
time
RT= 61.9–43.2 kΩ
2
μs
RT
Response
time
RT = 43.2–61.9 kΩ
3.5
μs
RT
Response
time
16
μs
ton
Minimum on-time
45
66
ns
toff
Minimum off-time
100
nsV
IN
(V)
VCC
(REG)
(V)
6
7
8
9
10
11
12
13
14
15
16
17 18
4.75
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
D005
Temperature (°C)
VCC
(UVLO)
(V)
-60
-40
-20
0
20
40
60
80
100
120 140
3.30
3.32
3.34
3.36
3.38
3.40
3.42
3.44
3.46
3.48
3.50
D006
V
IN
(V)
I
STANDBY
(
P
A)
8
9
10
11
12
13
14
15
16
17 18
25
30
35
40
45
50
55
60
65
70
D003
125
q
C
25
q
C
-40
q
C
Temperature (
q
C)
I
SHUTDOWN
(
P
A)
-50
-30
-10
10
30
50
70
90
110
130
150
0
2
4
6
8
10
12
D004D001
V
IN
8 V
V
IN
12 V
V
IN
18 V
Output Current (A)
Efficiency (%)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
20
30
40
50
60
70
80
90
100
D001
V
IN
8 V
V
IN
12 V
V
IN
18 V
Output Current (A)
Efficiency (%)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
20
30
40
50
60
70
80
90
100
D002
V
IN
8 V
V
IN
12 V
V
IN
18 V
9
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6.7 Typical Characteristics
At TA = 25oC, unless otherwise noted
VIN 8–18 V
EN = 12 V
2.2 MHz
VOUT 5 V
FPWM
Figure 1. Efficiency vs IOUT
VIN 8–18 V
EN = 12 V
2.2 MHz
VOUT 5 V
DEMB
Figure 2. Efficiency vs IOUT
EN = 12 V
Figure 3. ISTANDBY vs VIN
VIN 8–18 V
EN = 0 V
Figure 4. ISHUTDOWN vs Temperature
VIN 6-18 V
EN = GND
Figure 5. VCC(REG) vs VIN
VIN 8–18 V
EN = 12 V
Figure 6. VCC(UVLO) vs TemperatureOutput Current (A)
Output Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
3.22
3.23
3.24
3.25
3.26
3.27
3.28
3.29
3.3
3.31
3.32
D011
+125
q
C
+25
q
C
-40
q
C
Output Current (V)
Output Voltage (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
4.950
4.955
4.960
4.965
4.970
4.975
4.980
4.985
4.990
4.995
5.000
D012
+125
q
C
+25
q
C
-40
q
C
Temperature (
q
C)
CS Amplifier Gain (V/V)
-60
-40
-20
0
20
40
60
80
100
120 140
11.00
11.20
11.40
11.60
11.80
12.00
12.20
12.40
12.60
12.80
13.00
D010
Temperature (°C)
VCCX
(ON)
(V)
-60
-40
-20
0
20
40
60
80
100
120 140
4.00
4.05
4.10
4.15
4.20
4.25
4.30
4.35
4.40
4.45
4.50
D009
Temperature (°C)
VDDA
(REG)
(V)
-60
-40
-20
0
20
40
60
80
100
120 140
4.75
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
D007
Temperature (°C)
VDDA
(UVLO)
(V)
-60
-40
-20
0
20
40
60
80
100
120 140
3.10
3.12
3.14
3.16
3.18
3.20
3.22
3.24
3.26
3.28
3.30
D008
10
LM25141
SNVSAU1 –MARCH 2017
www.ti.com
Product Folder Links: LM25141
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Typical Characteristics (continued)
At TA = 25oC, unless otherwise noted
VCC Rising
EN = 12 V
Figure 7. VDD(REG) vs Temperature
VCC Rising
EN = 12 V
Figure 8. VDD(UVLO) vs Temperature
VCC Rising
EN = 12 V
Figure 9. VCCX(ON) vs Temperature
VIN 12 V
EN = 12 V
Figure 10. Current Sense Amplifier Gain vs Temperature
VIN 12 V
FB = VDDA
EN = 12 V
Figure 11. 3.3-V Output Voltage Regulation vs IOUT
VIN 12 V
EN = 12 V
FB = GND
Figure 12. 5-V Output Voltage Regulation vs IOUTTemperature ( C)°
Frequency (KHz)
-60
-40
-20
0
20
40
60
80
100
120
140
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
D017
RT 49.9 kΩ
RT 43.2 kΩ
RT 61.9 kΩ
Temperature (
q
C)
Frequency (KHz)
-60
-40
-20
0
20
40
60
80
100
120 140
200
240
280
320
360
400
440
480
520
560
600
D018
RT 49.9 k
:
RT 44.2 k
:
RT 73.2 k
:
Temperature (
q
C)
t
on
(ns)
-60
-40
-20
0
20
40
60
80
100
120 140
0
10
20
30
40
50
60
70
80
90
D015
Temperature (
q
C)
t
off
(ns)
-60
-40
-20
0
20
40
60
80
100
120 140
60
65
70
75
80
85
90
95
100
105
110
D016
Temperature (
q
C)
Frequency (KHz)
-60
-40
-20
0
20
40
60
80
100
120 140
2040
2100
2160
2220
2280
2340
2400
D013
Temperature (
q
C)
Frequency (KHz)
-60
-40
-20
0
20
40
60
80
100
120 140
410
415
420
425
430
435
440
445
450
455
460
465
470
D014
11
LM25141
www.ti.com
SNVSAU1 –MARCH 2017
Product Folder Links: LM25141
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
Typical Characteristics (continued)
At TA = 25oC, unless otherwise noted
VIN 12 V
EN = 12 V
OSC = VDDA
Figure 13. 2.2-MHz Oscillator Frequency vs Temperature
VIN 12 V
EN = 12 V
OSC = AGND
Figure 14. 440-kHz Oscillator Frequency vs Temperature
VIN 18 V
Figure 15. ton Minimum vs Temperature
VIN 3.8 V
VOUT 3.3 V
Figure 16. toff Minimum vs Temperature
VIN 12 V
Figure 17. RT Frequency vs Temperature (2.2 MHz)
VIN 12 V
Figure 18. RT Frequency vs Temperature (440 kHz)Copyright © 2016, Texas Instruments Incorporated
BIAS
VDDA
CONTROL
RESTART
LOGIC
HICCUP FAULT
TIMER 256 CYCLES
VIN
VCCX
VCC
VDDA
RES
OUT
CL
V
REF
1.2 V
20 uA
DEMB/
FPWM/
SYNIN
CLK
CL
+
CURRENT
LIMIT
75 mV
+
EN
CS
VOUT
Gain = 12
3.3 V
5 V
DEMB
OSC
RT
DITH
VOUT
DECODER/
MUX
+
SLOPE
COMPENSATION
RAMP
FB
STBY
SS
COMPLETE
20 uA
SS
SS
+
+
FBi
V
REF
1200 uS
+
COMP
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