SPC5606SF2VLQ6 微控制器 NXP

SPC5606SF2VLQ6

32位微控制器 - MCU 32BIT 1M FL 48K RAM

Document overview

This document describes the device features and highlights important electrical and physical characteristics. For functional characteristics, see the MPC5606S Microcontroller Reference Manual.

Description

The SPC5606SF2VLQ6 family of chips is designed to enable the development of automotive instrument cluster applications by providing a single-chip solution capable of hosting real-time applications and driving a TFT display directly using an on-chip color TFT display controller.

Flash memory 

The SPC5606SF2VLQ6 microcontroller has the following flash memory features:

• As nuch as 1 MB of burst flash memory

— Typical flash memory access time: 0 wait state for buffer hits, 2 wait states for page buffer miss at 64 MHz

— Two 4128-bit page buffers with programmable prefetch control

– One set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any access

– One set of page buffers allocated to Display Controller Unit and the eDMA

— 64-bit ECC with single-bit correction, double-bit detection for data integrity

— 64 KB data flash memory — separate 416 KB flash block for EEPROM emulation with prefetch buffer and 128-bit data access port

Memory Protection Unit (MPU) SPC5606SF2VLQ6

The MPU features the following:

• 12 region descriptors for per-master protection

• Start and end address defined with 32-byte granularity

• Overlapping regions supported

• Protection attributes can optionally include process ID

• Protection offered for three concurrent read ports

• Read and write attributes for all masters

• Execute and supervisor/user mode attributes for processor masters