供应TMS320F206PZA 嵌入式 - DSP（数字式信号处理器） （停产）

类别集成电路（IC）产品族嵌入式 - DSP（数字式信号处理器）系列TMS320C20x

规格类型定点接口SSP，UART时钟速率40MHz非易失性存储器闪存（64 kB）片载 RAM9kB电压 - I/O5.00V电压 - 内核5.00V工作温度-40°C ~ 85°C（TA）安装类型表面贴装封装/外壳100-LQFP供应商器件封装100-LQFP（14x14）

High-Performance Static CMOS Technology

Includes the T320C2xLP Core CPU

TMS320F206 is a Member of the

TMS320C20x Generation, Which Also

Includes the TMS320C203, and

TMS320C209 Devices

Instruction-Cycle Time 50 ns @ 5 V

Source Code Compatible With TMS320C25

Upwardly Code-Compatible With

TMS320C5x Devices

Three External Interrupts

TMS320F206 Integrated Memory:

– 544 × 16 Words of On-Chip Dual-Access

Data RAM

– 32K × 16 Words of On-Chip Flash

Memory (EEPROM)

– 4K × 16 Words of On-Chip Single-Access

Program/Data RAM

224K × 16-Bit Maximum Addressable

External Memory Space

– 64K Program

– 64K Data

– 64K Input/Output (I/O)

– 32K Global

32-Bit ALU/Accumulator

16 × 16-Bit Multiplier With a 32-Bit Product

Block Moves from Data and Program

Space

TMS320F206 Peripherals:

– On-Chip 16-Bit Timer

– On-Chip Software-Programmable

Wait-State (0 to 7) Generator

– On-Chip Oscillator

– On-Chip Phase-Locked Loop (PLL)

– Six General-Purpose I/O Pins

– Full-Duplex Asynchronous Serial Port

(UART)

– Enhanced Synchronous Serial Port

(ESSP) With Four-Level-Deep FIFOs

Input Clock Options

– Options – Multiply-by-One, -Two, or -Four

and Divide-by-Two

Support of Hardware Wait States

Power Down IDLE Mode

IEEE 1149.1†-Compatible Scan-Based

Emulation

100-Pin Thin Quad Flat Package (TQFP)

(PZ Suffix)